1.4. GTS Ethernet Intel® FPGA Hard IP v6.0.0
| Quartus® Prime Version | Description | Impact |
|---|---|---|
| 24.3 | Device support for Agilex™ 5 D-Series is no longer restricted. | Supports Simulation, Compilation, and Timing (SCT) only. |
| Added support for Aldec Riviera-PRO* simulation tool. | — | |
| Added hardware support for AN/LT and PTP IEEE 1588v2 for Agilex™ 5 E-Series device group B FPGAs. | — | |
| Removed o_rx_am_lock signal. | You need to modify the IP instantiation in the top-level. |