1.1. MIPI D-PHY IP for Agilex™ 3 and Agilex™ 5 FPGAs v6.0.0

MIPI D-PHY IP Release Notes: Agilex™ 3 and Agilex™ 5 FPGAs

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ID 817563

Date 7/07/2025

Version

Public

1.1. MIPI D-PHY IP for Agilex™ 3 and Agilex™ 5 FPGAs v6.0.0

Table 1. v6.0.0 2025.07.07
Description	Impact
Added support for Agilex™ 3 devices.	-
Added hardware support for Agilex™ 5 devices	-

Table 2. Agilex 3 C-Series Device MIPI D-PHY IP Speed Support Summary
Subcategory	Max Rate (Mbps)		-6				-7
Subcategory	-6	-7	S	C	T	H	S	C	T	H
Long reference/standard reference/ short reference¹	150 - 2,500¹	150 - 2,500¹	X	X	X²	X	X	X	X²	X³
Support level key: S = simulation support C = compilation support T = timing support H = hardware support X = supported feature. An empty table cell indicates that the feature is not currently supported. ¹ = Long reference/standard reference/short reference is reference to the insertion loss condition from MIPI Alliance D-PHY specifications. ² = Timing is preliminary. You must recompile the design in future releases. ³ = Hardware support is available for M16A packages.

Table 3. Agilex™ 3 C-Series FPGA MIPI D-PHY IP Feature Support Summary
Protocol	Category	Sub-Category	Supported?	S	C	T	H
MIPI D-PHY	PPI bus width	16	X	X	X	X	X
	Skew Calibration	RX and TX	X	X	X	X	X
	Alternate Calibration	RX and TX	X	X	X	X	X
	Periodic Calibration	TX	X	X	X	X	X
	Design Example		X	X	X	X	X
	TX Equalization Mode	Medium LP	X	X	X	X	X
		High LP	X	X	X	X	X
		Medium CZ	X	X	X	X	X
	RX Equalization Mode	Small	X	X	X	X	X
		Medium	X	X	X	X	X
		Large	X	X	X	X	X
	Simulation	External loopback simulation	X	X
	Simulators ¹	VCS-MX	X	X
		QuestaSim	X	X
		Xcelium	X	X
		Questa-Intel FPGA Edition	X	X
		Aldec Riviera-Pro
Support level key: S = simulation support C = compilation support T = timing support H = hardware support X = supported feature. ¹ = VHDL is not supported.

Table 4. Agilex™ 5 D-Series FPGA MIPI D-PHY IP Speed Support Summary
		Max Rate (Mbps)			-1				-2				-3
Device Family	Subcategory	-1	-2	-3	S	C	T	H	S	C	T	H	S	C	T	H
D Series Device	standard reference / short reference ¹	150 - 3500¹	150 - 3500¹	150 - 3500¹	X	X	X³	-	X	X	X³	-	X	X	X³	-
D Series Device	Long reference ²	150 - 2500²	150 - 2500²	150 - 2500²	X	X	X³	-	X	X	X³	-	X	X	X³	-
Support level key: S = simulation support C = compilation support T = timing support H = hardware support X = supported feature. An empty table cell indicates that the feature is not currently supported. ¹ = Standard reference/short reference is reference to the insertion loss condition from MIPI Alliance D-PHY specifications. ² = Long reference is reference to the insertion loss condition from MIPI Alliance D-PHY specifications. ³ = Timing is currently preliminary. It will be necessary to recompile in future releases.

Table 5. Agilex™ 5 D-Series FPGA MIPI D-PHY IP Feature Support Summary
Protocol	Category	Sub-Category	Supported?	S	C	T	H
MIPI D-PHY	PPI bus width	16	X	X	X	X
	Skew Calibration	RX and TX	X	X	X	X
	Alternate Calibration	RX and TX	X	X	X	X
	Periodic Calibration	TX	X	X	X	X
	Design Example		X	X	X	X
	TX Equalization Mode	Medium LP	X	X	X	X
		High LP	X	X	X	X
		Medium LP	X	X	X	X
	RX Equalization Mode	Small	X	X	X	X
		Medium	X	X	X	X
		Large	X	X	X	X
	Simulation	External loopback simulation	X	X
	Simulators ¹	VCS-MX	X	X
		QuestaSim	X	X
		Xcelium	X	X
		Questa-Intel FPGA Edition	X	X
		Aldec Riviera-Pro
Support level key: S = simulation support C = compilation support T = timing support H = hardware support X = supported feature. ¹ = VHDL is not supported.

Table 6. Agilex™ 5 E-Series FPGA Device Group A MIPI D-PHY IP Speed Support Summary
		Max Rate (Mbps)			-1				-2				-3
Device Family	Subcategory	-1	-2	-3	S	C	T	H	S	C	T	H	S	C	T	H
E Series Device Group A	standard reference / short reference ¹	150 - 3500¹	150 - 3500¹	150 - 3500¹	X	X	X³	-	X	X	X³	-	X	X	X³	-
E Series Device Group A	Long reference ²	150 - 2500²	150 - 2500²	150 - 2500²	X	X	X³	-	X	X	X³	-	X	X	X³	-
Support level key: S = simulation support C = compilation support T = timing support H = hardware support X = supported feature. An empty table cell indicates that the feature is not currently supported. ¹ = Standard reference/short reference is reference to the insertion loss condition from MIPI Alliance D-PHY specifications. ² = Long reference is reference to the insertion loss condition from MIPI Alliance D-PHY specifications. ³ = Timing is currently preliminary. It will be necessary to recompile in future releases.

Table 7. Agilex™ 5 E-Series FPGA Device Group A MIPI D-PHY IP Feature Support Summary
Protocol	Category	Sub-Category	Supported?	S	C	T	H
MIPI D-PHY	PPI bus width	16	X	X	X	X
	Skew Calibration	RX and TX	X	X	X	X
	Alternate Calibration	RX and TX	X	X	X	X
	Periodic Calibration	TX	X	X	X	X
	Design Example		X	X	X	X
	TX Equalization Mode	Medium LP	X	X	X	X
		High LP	X	X	X	X
		Medium LP	X	X	X	X
	RX Equalization Mode	Small	X	X	X	X
		Medium	X	X	X	X
		Large	X	X	X	X
	Simulation	External loopback simulation	X	X
	Simulators ¹	VCS-MX	X	X
		QuestaSim	X	X
		Xcelium	X	X
		Questa-Intel FPGA Edition	X	X
		Aldec Riviera-Pro
Support level key: S = simulation support C = compilation support T = timing support H = hardware support X = supported feature. ¹ = VHDL is not supported.

Table 8. Agilex™ 5 E-Series FPGA Device Group B MIPI D-PHY IP Speed Support Summary
		Max Rate (Mbps)			-4				-5				-6
Device Family	Subcategory	-4	-5	-6	S	C	T	H	S	C	T	H	S	C	T	H
E Series Device Group B	long reference / standard reference / short reference ¹	150 - 2500¹	150 - 2500¹	150 - 2500¹	X	X	X²	X	X	X	X²	X	X	X	X²	X
Support level key: S = simulation support C = compilation support T = timing support H = hardware support X = supported feature. An empty table cell indicates that the feature is not currently supported. ¹ = Long reference/standard reference/short reference is reference to the insertion loss condition from MIPI Alliance D-PHY specifications. ² = Timing is currently preliminary. It will be necessary to recompile in future releases.

Table 9. Agilex™ 5 E-Series FPGA Device Group B MIPI D-PHY IP Feature Support Summary
Protocol	Category	Sub-Category	Supported?	S	C	T	H
MIPI D-PHY	PPI bus width	16	X	X	X	X	X
	Skew Calibration	RX and TX	X	X	X	X	X
	Alternate Calibration	RX and TX	X	X	X	X	X
	Periodic Calibration	TX	X	X	X	X	X
	Design Example		X	X	X	X	X
	TX Equalization Mode	Medium LP	X	X	X	X	X
		High LP	X	X	X	X	X
		Medium CZ	X	X	X	X	X
	RX Equalization Mode	Small	X	X	X	X	X
		Medium	X	X	X	X	X
		Large	X	X	X	X	X
	Simulation	External loopback simulation	X	X
	Simulators ¹	VCS-MX	X	X
		QuestaSim	X	X
		Xcelium	X	X
		Questa-Intel FPGA Edition	X	X
		Aldec Riviera-Pro
Support level key: S = simulation support C = compilation support T = timing support H = hardware support X = supported feature. ¹ = VHDL is not supported.