External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817394
Date 3/31/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP 4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Agilex™ 5 EMIF IP 2.7. Compiling the Agilex™ 5 EMIF Design Example 2.8. Using the Design Example with the Test Engine IP 2.9. Generating the EMIF Design Example with the Performance Monitor
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS Group for x32+ECC DDR4 Interface 2.3.2. Example: Byte Swizzling for x32 DDR4 Interface, Using a Memory Device of x8 Width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for x32 + ECC DDR4 Interface 2.3.5. Example: Swizzling for a 2-Channel x32 + ECC Interface 2.3.6. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

1.1. Release Information

IP versions are the same as the Quartus® Prime Design Suite software versions up to v19.1. From Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.

The IP versioning scheme (X.Y.Z) number changes from one software version to another. A change in:

  • X indicates a major revision of the IP. If you update your Quartus® Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Note: This documentation is preliminary and subject to change.
IP Name IP Version Quartus® Prime Release Date
External Memory Interfaces (EMIF) IP - DDR4 Component 3.0.0 25.1 2025.03.31
External Memory Interfaces (EMIF) IP - DDR4 DIMM 3.0.0 25.1 2025.03.31
External Memory Interfaces (EMIF) IP - DDR5 Component 3.0.0 25.1 2025.03.31
External Memory Interfaces (EMIF) IP - DDR5 DIMM 3.0.0 25.1 2025.03.31
External Memory Interfaces (EMIF) IP - LPDDR4 Component 3.0.0 25.1 2025.03.31
External Memory Interfaces (EMIF) IP - LPDDR5 Component 3.0.0 25.1 2025.03.31
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