External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817394
Date 1/13/2025
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP 4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Agilex™ 5 EMIF IP 2.7. Compiling the Agilex™ 5 EMIF Design Example 2.8. Using the Design Example with the Test Engine IP 2.9. Generating the EMIF Design Example with the Performance Monitor
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS Group for x32+ECC DDR4 Interface 2.3.2. Example: Byte Swizzling for x32 DDR4 Interface, Using a Memory Device of x8 Width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for x32 + ECC DDR4 Interface 2.3.5. Example: Swizzling for a 2-Channel x32 + ECC Interface 2.3.6. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

2.3.5. Example: Swizzling for a 2-Channel x32 + ECC Interface

Table 11.  Byte Swizzling for an RDIMM DDR5 2Ch x 32 + ECC Interface Implemented with Ch0 Top Sub-bank / Ch1 Bottom Sub-bank
Scheme BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
Default Placement GPIO DQ[ECC] DQ[3] DQ[2] AC0 AC1 DQ[0] DQ[1]
DQS Group Number in Byte Swizzling Notation X ECC 3 2 X X 0 1
After Byte Swizzle X ECC 3 2 X X 1 0
 
Default Placement DQ[1] DQ[0] AC0 AC1 DQ[2] DQ[3] DQ[ECC} GPIO
DQS Group Number in Byte Swizzling Notation 1 0 X X 2 3 ECC X
After Byte Swizzle 1 0 X X 3 2 ECC X

This example illustrates byte swizzling in Ch0 DQS group 1 (BL7) with DQS group 0 (BL6), and Ch1 DQS Group 2 (BL4) with DQS group 3 (BL5). To achieve this swizzling, enter the following BYTE_SWIZZLE_CH0 and BYTE_SWIZZLE_CH1 specifications in the Pin Swizzle Map under the PHY section in the External Memory Interfaces IP parameter editor.

  • BYTE_SWIZZLE_CH0=X,ECC,3,2,X,X,1,0; 
  • BYTE_SWIZZLE_CH0=1,0,X,X,3,2,ECC,X;
Table 12.  Example of DQ Pin Swizzling in Ch0 ECC Lane for a 2Ch x 32 + ECC Interface
Lane Pin Index Default Placemnent After Swizzling
BL3 47 MEM_DQ[23] MEM_DQ[23]
46 MEM_DQ[22] MEM_DQ[22]
45 MEM_DQ[21] MEM_DQ[21]
44 MEM_DQ[20] MEM_DQ[20]
43    
42 MEM_DM_N[4] MEM_DM_N[4]
41 MEM_DQS_C[4] MEM_DQS_C[4]
40 MEM_DQS_T[4] MEM_DQS_T[4]
39 MEM_DQ[19] MEM_DQ[16]
38 MEM_DQ[18] MEM_DQ[19]
37 MEM_DQ[17] MEM_DQ[18]
36 MEM_DQ[16] MEM_DQ[17]
BL1 23 MEM_DQ[39] MEM_DQ[36]
22 MEM_DQ[38] MEM_DQ[37]
21 MEM_DQ[37] MEM_DQ[38]
20 MEM_DQ[36] MEM_DQ[39]
19    
18 MEM_DM_N[4] MEM_DM_N[4]
17 MEM_DQS_C[4] MEM_DQS_C[4]
16 MEM_DQS_T[4] MEM_DQS_T[4]
15 MEM_DQ[35] MEM_DQ[34]
14 MEM_DQ[34] MEM_DQ[35]
13 MEM_DQ[33] MEM_DQ[32]
12 MEM_DQ[32] MEM_DQ[33]

To achieve the pin swizzling shown in the table above, enter the following PIN_SWIZZLE_CH0 specifications in the PHY section of the Pin Swizzle Map:

PIN_SWIZZLE_CH0_ECC=1,0,3,2,7,6,5,4;

This is a full ECC byte but because it is implemented with x4 devices, it must follow the x4 restrictions of placing the lower 4 bits of the byte in the lower half and the upper four bits of the byte in the upper half:

  • BYTE_SWIZZLE_CH0_DQS4=17,18,19,16;
  • BYTE_SWIZZLE_CH0_DQS5=21,20,22,23;

For x4 device widths, the values in BYTE_SWIZZLE represent the bundles of 2 x4 DQS groups. The lower DQS group of the bundle is connected to the lower half of the byte lane, whereas the upper DQS group of the bundle is connected to the upper half of the byte lane.

The placement of each DQS bundle and DQS group in this example, after the byte swizzling, follows the pattern as shown below:

  • Ch0 Bundle 2 is placed on BL3:
    • Ch0 DQS4 connected to the lower half on BL3
    • Ch0 DQS5 connected to the upper half on BL3
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