GTS CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 814583
Date 3/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document History for GTS CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL 2.2.8. Reset Sequencer
1. Quick Start Guide
2. Design Example Description
3. GTS CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document History for GTS CPRI PHY Intel® FPGA IP Design Example User Guide

2.6. Design Example Registers

Table 23.  Design Example Registers
Channel Number Base Address

(Byte Address)

 Register Type
0 0x00000000 CPRI PHY reconfiguration interface registers for Channel 0
0x00100000 Datapath and PMA Avalon® memory-mapped interface registers for Channel 0
1 0x01000000 CPRI PHY reconfiguration interface registers for Channel 1
0x01100000 Datapath Avalon® memory-mapped interface registers for Channel 1
2 0x02000000 CPRI PHY reconfiguration registers for Channel 2
0x02100000 Datapath Avalon® memory-mapped interface registers for Channel 2
3 0x03000000 CPRI PHY reconfiguration interface registers for Channel 3
0x03100000 Datapath Avalon® memory-mapped interface registers for Channel 3
Level Two Title