GTS CPRI PHY Intel® FPGA IP User Guide

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ID 814577
Date 8/15/2024
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Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY FPGA IP 2. Getting Started 3. GTS CPRI PHY IP Parameter Settings 4. Functional Description 5. Interface Signals 6. GTS CPRI PHY IP Registers 7. GTS CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide
1. About the GTS CPRI PHY FPGA IP x
1.1. GTS CPRI PHY IP Features 1.2. GTS CPRI PHY IP Device Family Support 1.3. GTS CPRI PHY IP Device Speed Grade Support 1.4. GTS CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Specifying the GTS CPRI PHY IP Parameters and Options 2.3. Generated File Structure 2.4. GTS CPRI PHY IP Testbenches
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the GTS CPRI PHY IP Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
3. GTS CPRI PHY IP Parameter Settings x
3.1. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency
5. Interface Signals x
5.1. GTS CPRI PHY IP Clock Signals 5.2. GTS CPRI PHY IP Reset Signals 5.3. GTS CPRI PHY IP TX MII (64b/66b) 5.4. GTS CPRI PHY IP RX MII (64b/66b) 5.5. GTS CPRI PHY IP Status Interface for 64b/66b Line Rate 5.6. GTS CPRI PHY IP TX Interface (8b/10b) 5.7. GTS CPRI PHY IP RX Interface (8b/10b) 5.8. GTS CPRI PHY IP Status Interface for 8b/10b Line Rate 5.9. GTS CPRI PHY IP Serial Interface 5.10. GTS CPRI PHY Reconfiguration Interface 5.11. GTS CPRI PHY IP Datapath and PMA Avalon Memory-Mapped Interface
5.1. GTS CPRI PHY IP Clock Signals x
5.1.1. GTS CPRI PHY IP Required Clock Frequencies
1. About the GTS CPRI PHY FPGA IP
2. Getting Started
3. GTS CPRI PHY IP Parameter Settings
4. Functional Description
5. Interface Signals
6. GTS CPRI PHY IP Registers
7. GTS CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide

5.1.1. GTS CPRI PHY IP Required Clock Frequencies

Table 17.  GTS CPRI PHY IP Required Clock Frequencies
Port Name Frequency (MHz) Notes
i_reconfig_clk 100 Provides control and status register access on all the Avalon® memory-mapped interfaces.
o_tx_clkout 245.76 System clock divided by 2.
o_tx_clkout2 153.6 CPRI PHY system clock times (64/66) for 10G channels.
245.76 Line rate TX PLL div40 for 9.8G line rate
153.6 Line rate TX PLL div40 for 6G line rate
245.76 CPRI PHY system clock for 4.9G channels.
153.6 CPRI PHY system clock for 3G channels.
122.88 CPRI PHY system clock for 2.4G channels.
61.44 CPRI PHY system clock for 1.2G channels.
o_rx_clkout

245.76

 System clock divided by 2
o_rx_clkout2 153.6 Derived from recovered clock for 10G channels.
245.76 Line rate TX PLL div40 for 9.8G line rate
153.6 Line rate TX PLL div40 for 6G line rate
245.76 Derived from recovered clock for 4.9G channels.
153.6 Derived from recovered clock for 3G channels.
122.88 Derived from recovered clock for 2.4G channels.
61.44 Derived from recovered clock for 1.2G channels.
i_sampling_clk 250 Sampling clock for deterministic logic from external source.
o_cdr_divclk 46.08

Derived from reference clock of 184.32 MHz for 10G channels (refclk/N, N=4).

Applicable for 64B/66B line rates

38.4

Derived from reference clock of 153.6 MHz for 9.8G, 6G, 4.9G, 3G, 2.4G, and 1.2G channels (refclk/N, N=4).

Applicable for 8B/10B line rates

30.7

Derived from reference clock of 122.88 MHz for 10G, 4.9G, 3G, 2.4G, and 1.2G channels (refclk/N, N=4).

Applicable for all line rates.
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