GTS JESD204C Intel® FPGA IP Design Example User Guide

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ID 813978
Date 5/09/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C Intel® FPGA IP Design Example User Guide 2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the GTS JESD204C Design Example 4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide
2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Dual Simplex Design Example 2.5. Simulating the Design Example Testbench 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.4. Dual Simplex Design Example x
2.4.1. Dual Simplex Parameter Description 2.4.2. Generating Dual Simplex Design Example
3. Detailed Description for the GTS JESD204C Design Example x
3.1. System Components 3.2. GTS JESD204C Design Example Clock and Reset 3.3. GTS JESD204C Design Example Signals 3.4. GTS JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. Pattern Generator and Checker 3.1.9. GTS JESD204C TX and RX IP
1. About the GTS JESD204C Intel® FPGA IP Design Example User Guide
2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the GTS JESD204C Design Example
4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide

4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2025.05.09 25.1 6.0.0
  • Updated sections:
    • Hardware and Software Requirements
    • Dual Simplex Design Example
    • Simulating the Design Example Testbench
  • Updated Figures:
    • Directory Structure for GTS JESD204C Agilex 5 Design Example
    • Clock Control GUI Settings
  • Updated Table: Directory Files
  • Added sections:
    • Dual Simplex Parameter Description
    • Generating Dual Simplex Design Example
2024.12.13 24.3 4.0.0
  • Updated sections:
    • GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide
    • Hardware and Software Requirements
  • Updated Table: Parameters in the Example Design Tab
  • Updated figures:
    • Development Stages for the Design Example
    • Directory Structure for GTS JESD204C Agilex 5 Design Example
    • Timing Diagram for the Design Example Resets
  • Added sections:
    • Compiling and Testing the Design
    • Hardware Test for System Console Control Design Example
    • Dual Simplex Design Example
  • Removed section Compiling the Design Example
2024.07.12 24.2 3.0.0 Updated the following sections to remove VCS* support:
  • Software Requirements
  • Directory Structure
  • Simulating the Design Example Testbench
2024.04.01 24.1 2.0.0 Initial release.
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