General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs
ID
813934
Date
8/04/2025
Public
1. Agilex™ 5 General-Purpose I/O Overview
2. Agilex™ 5 HSIO Banks
3. Agilex™ 5 HVIO Banks
4. Agilex™ 5 HPS I/O Banks
5. Agilex™ 5 SDM I/O Banks
6. Agilex™ 5 I/O Troubleshooting Guidelines
7. GPIO FPGA IP
8. Programmable I/O Features Description
9. Document Revision History for the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os
2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank
2.5.3. VREF Sources and Input Standards Grouping
2.5.4. HSIO Pin Restrictions for External Memory Interfaces
2.5.5. RZQ Pin Requirement
2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.8. Simultaneous Switching Noise
2.5.9. HPS Shared I/O Requirements
2.5.10. Clocking Requirements
2.5.11. Clock Restrictions for GPIO Interfaces
2.5.12. SDM Shared I/O Requirements
2.5.13. Unused Pins
2.5.14. VCCIO_PIO Supply for Unused HSIO Banks
2.5.15. HSIO Pins During Power Sequencing
2.5.16. Drive Strength Requirement for HSIO Input Pins
2.5.17. Maximum DC Current Restrictions
2.5.18. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility
2.5.19. Connection to True Differential Signaling Input Buffers During Device Reconfiguration
2.5.20. LVSTL700 I/O Standards Differential Pin Pair Requirements
2.5.21. Implementing a Pseudo Open Drain
2.5.22. Allowed Duration for Using RT OCT
2.5.23. Single-Ended Strobe Signal Differential Pin Pair Restriction
2.5.24. Implementing SLVS-400 or DPHY I/O Standard with 1.1 V VCCIO_PIO
7.5.1. GPIO FPGA IP Data Paths
Figure 39. High-Level View of Single-Ended I/O
Data Path | Register Mode | ||
---|---|---|---|
Bypass | Simple Register | DDIO | |
Input | Data goes from the delay element to the core, bypassing all double data rate I/Os (DDIOs). | The DDIO operates as a simple register. The Fitter chooses whether to pack the register in the I/O or implement the register in the core, depending on the area and timing trade-offs. | The DDIO operates as a regular DDIO. |
Output | Data goes from the core straight to the delay element, bypassing all DDIOs. | ||
Bidirectional | The output buffer drives both an output pin and an input buffer. | The DDIO operates as a simple register. The output buffer drives both an output pin and an input buffer. | The DDIO operates as a regular DDIO. The output buffer drives both an output pin and an input buffer. The input buffer drives a set of three flip-flops. |
If you use asynchronous clear and preset signals, all DDIOs share these same signals.