MIPI CSI-2 Intel® FPGA IP Design Example User Guide

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ID 813931
Date 3/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide 2. MIPI CSI-2 Intel® FPGA IP Design Example 3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Directory Structure 1.4. Compiling the Design
1.1. Generating the Design x
1.1.1. Design Example Parameters
2. MIPI CSI-2 Intel® FPGA IP Design Example x
2.1. Agilex™ 5 MIPI CSI-2 RX+TX Design 2.2. Agilex™ 5 MIPI CSI-2 RX-only Design 2.3. Software Requirements 2.4. Functional Description 2.5. Simulation
2.4. Functional Description x
2.4.1. MIPI CSI-2 Design Components 2.4.2. MIPI CSI-2 IP Design Example Reset Scheme 2.4.3. MIPI CSI-2 IP Design Example Clocking Scheme
2.5. Simulation x
2.5.1. Data Signal Checking 2.5.2. Verification 2.5.3. Display Messages 2.5.4. Plotting Waveforms 2.5.5. Structure 2.5.6. Known Limitations
2.5.5. Structure x
2.5.5.1. Top Level Testbench 2.5.5.2. PHY-Protocol Interface (PPI) Loopback 2.5.5.3. Test Generator
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide
2. MIPI CSI-2 Intel® FPGA IP Design Example
3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide

2.5.6. Known Limitations

The MIPI CSI-2 IP Design Example has the following known limitations:
  • Xcelium is not supported.
  • Aldec Riviera-PRO is only supported for fast Simulations.
  • Passthrough mode simulation is only supported in loopback fast simulations.
  • Passthrough mode is not supported for 8-lane configurations in A5E 005B devices because of insufficient memory resources.
  • The B18A package provides a limited number of lanes for D-PHY interfaces, with available bonded pins between BYTE4 to BYTE7. Conflicts may arise between the RZQ pin and data lane pins. For placement rules, refer to MIPI D-PHY User Guide
  • YUV420 has limited support for 4-D-PHY and 8-D-PHY lanes (1C & 4D and 1C & 8D). Full simulation does not support 8-D-PHY lanes
Level Two Title