MIPI CSI-2 Intel® FPGA IP Design Example User Guide

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ID 813931
Date 3/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide 2. MIPI CSI-2 Intel® FPGA IP Design Example 3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Directory Structure 1.4. Compiling the Design
1.1. Generating the Design x
1.1.1. Design Example Parameters
2. MIPI CSI-2 Intel® FPGA IP Design Example x
2.1. Agilex™ 5 MIPI CSI-2 RX+TX Design 2.2. Agilex™ 5 MIPI CSI-2 RX-only Design 2.3. Software Requirements 2.4. Functional Description 2.5. Simulation
2.4. Functional Description x
2.4.1. MIPI CSI-2 Design Components 2.4.2. MIPI CSI-2 IP Design Example Reset Scheme 2.4.3. MIPI CSI-2 IP Design Example Clocking Scheme
2.5. Simulation x
2.5.1. Data Signal Checking 2.5.2. Verification 2.5.3. Display Messages 2.5.4. Plotting Waveforms 2.5.5. Structure 2.5.6. Known Limitations
2.5.5. Structure x
2.5.5.1. Top Level Testbench 2.5.5.2. PHY-Protocol Interface (PPI) Loopback 2.5.5.3. Test Generator
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide
2. MIPI CSI-2 Intel® FPGA IP Design Example
3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide

1.3. Directory Structure

The Quartus® Prime software generates the MIPI CSI-2 IP design example files in various directories that the following tables describe.
Table 3.  Generated Files in the quartus Directory and File DescriptionsThe quartus directory contains the Quartus Prime project files, including compilation reports:
File Description
csi2_dphy_sys.qpf Quartus Prime project file.
csi2_dphy_sys.qsf Quartus Prime .qsf assignment file.
Table 4.  Generated Files in the rtl Directory and File Descriptions for Synthesis and Full SimulationsThe rtl directory contains all synthesizable components, including the system interconnect and Platform Designer generated IP:
Directory or File Description
csi2_dphy_sys.qsys Platform Designer file that contains CSI-2 and DPHY system definition.
csi2_dphy_sys/ Directory that contains Platform Designer generated files.
synth/csi2_dphy_sys.v Top-level subsystem wrapper Verilog HDL file.
ip/ Directory that contains all files for the IP in the csi2_dphy_sys system.
csi2_dphy_sys_csi2_rx.ip IP definition file for MIPI CSI-2 RX.
csi2_dphy_sys_csi2_tx.ip IP definition file for MIPI CSI-2 TX.
csi2_dphy_sys_mipi_dphy.ip IP definition file for MIPI D-PHY.
csi2_dphy_sys_csi2_reset_release_0.ip IP definition file for Reset Release.
csi2_dphy_sys_axi_clock_bridge.ip IP definition file for Clock Bridge for AXI4S Clock.
csi2_dphy_sys_dphy_clock_bridge.ip IP definition file for Clock Bridge for DPHY Clock.
csi2_dphy_sys_csi2_rx/synth/csi2_dphy_sys_csi2_rx.v MIPI CSI-2 RX IP wrapper Verilog HDL file.
csi2_dphy_sys_csi2_tx/synth/csi2_dphy_sys_csi2_tx.v MIPI CSI-2 TX IP wrapper Verilog HDL file.
csi2_dphy_sys_mipi_dphy/synth /csi2_dphy_sys_mipi_dphy.v MIPI D-PHY IP wrapper Verilog HDL file.
csi2_dphy_sys_csi2_reset_release_0/synth/ csi2_dphy_sys_csi2_reset_release_0.v Reset Release IP wrapper Verilog HDL file.
csi2_dphy_sys_axi_clock_bridge/synth/ csi2_dphy_sys_axi_clock_bridge.v AXI4S Clock Bridge IP wrapper Verilog HDL file.
csi2_dphy_sys_dphy_clock_bridge/synth/ csi2_dphy_sys_dphy_clock_bridge.v DPHY Clock Bridge IP wrapper Verilog HDL file.
Table 5.  Generated Files in the rtl Directory and File Descriptions for Fast SimulationsThe rtl directory contains all synthesizable components, including the system interconnect and Platform Designer generated IP:
Directory or File Description
csi_tx_rx_sys.qsys Platform Designer file that contains CSI-2 system definition.
csi_tx_rx_sys/ Directory that contains Platform Designer generated files.
synth/csi_tx_rx_sys.v Top-level subsystem wrapper Verilog HDL file.
ip/ Directory that contains all files for the IP in the csi_tx_rx_sys system.
csi_tx_rx_sys_csi2_rx.ip IP definition file for MIPI CSI-2 RX.
csi_tx_rx_sys_csi2_tx.ip IP definition file for MIPI CSI-2 TX.
csi_tx_rx_sys_csi2_rx/synth/csi_tx_rx_sys_csi2_rx.v MIPI CSI-2 RX IP wrapper Verilog HDL file.
csi_tx_rx_sys_csi2_tx/synth/csi_tx_rx_sys_csi2_tx.v MIPI CSI-2 TX IP wrapper Verilog HDL file.
Table 6.  Generated Files in ed_sim Directory and File DescriptionsThe ed_sim directory contains all simulation files and scripts:
Directory / File Description
ed_sim_tb.sv Top-level testbench file.
dut_wrapper.sv Wrapper around MIPI CSI-2 TX, RX and PPI Loopback.
cfg_pkg.sv SystemVerilog package containing generated IP parameters.
sim.spd File used by Quartus Prime ip-make-simscript.
hdl/ Contains Encrypted Verification IP files.
sim/aldec/ Contains Riviera-PRO simulator script.
run_rivierapro_setup.tcl Script that runs Riviera-PRO simulation.
rivierapro_setup.tcl Setup file for Riviera-PRO simulation.
sim/mentor/ Contains Mentor simulator script.
run_msim_setup.tcl Script that runs Questa simulation.
msim_setup.tcl Setup file for Questa simulation.
sim/synopsys/vcsmx/ Contains Synopsys VCS-MX simulator script.
sim.sh Script that runs VCS-MX simulation
vcsmx_setup.sh Setup script for VCS-MX simulation.
synopsys_sim_setup.sh Setup file for VCS-MX simulation.
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