Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 2/21/2025
Public

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4.2.2. Features

Table 32.  FIFO Intel® FPGA IP Cores Features
FIFO Intel® FPGA IP Cores Features
SCFIFO
  • Single-clock for read and write operations.
DCFIFO
  • Dual-clock for read and write operations.
  • Same read and write port widths.
DCFIFO_MIXED_WIDTHS
  • Dual-clock for read and write operations.
  • Different read and write port widths.
  • Valid read-write width ratio values of 1, 2, 4, 8, 16, and 32.