Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 9/03/2024
Public
Document Table of Contents

3.10. Consider Registering the Memory Output

Using registered outputs in your memory design can enhance timing closure, enable pipeline stages for improved performance, and facilitate synchronization in memory blocks, leading to higher overall system performance.

For more information, please refer to Use Synchronous Memory Blocks in the Intel Quartus Prime Pro Edition User Guide: Design Recommendations.