Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs

ID 813773
Date 9/29/2025
Public
Document Table of Contents

8. Document Revision History for the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs

Document Version Quartus® Prime Version Changes
2025.09.29 25.1
  • Updated content to reflect that the default setting is enabled instead of disabled in the Generating Compressed .sof File section.
  • Updated the values for A5E 043, A5E 052, A5E 065 in the Configuration Time for Various Configuration Modes table in the Configuration Time Estimation section.
2025.03.31 25.1
  • Added information regarding QSPI ownership between SDM and HPS in the AS Configuration section.
  • Added rows for the following to the Parallel Flash Loader II FPGA Configuration Parameters table in the Parallel Flash Loader II IP Parameters section.
    • What is the page access time?
    • Maximum timing requirement for nCONFIG high to nSTATUS high
  • Removal of GTS transceivers from the Additional Clock Requirements for HPS section.
  • Added "must be set to 0" in the Command and Response Header Description table in the Commands and Responses section.
2025.01.23 24.3.1
  • Added A5E 008 and A5E 013 to the Configuration Time for Various Configuration Modes table.
  • Added link to the SmartVID Debug Checklist and Voltage Regulator Guidelines in the SDM I/O Pins for Power Management and SmartVID and Configuration Debugging Checklist sections.
2024.11.04 24.3
  • Added list to first paragraph of OSC_CLK_1 Requirements in the OSC_CLK_1 Clock Input section.
  • Updated Word 5 for CONFIG_STATUS in the Command List and Description table in the Operation Commands section. .
  • Updated the descriptions for the following commands in the Command List and Description table in the Operation Commands section.
    • QSPI_ERASE
    • CONFIG_STATUS
  • Changed the command header field from Client to Reserved in the Commands and Responses section.
  • Updated the nINIT_DONE signal in the Power-On, Configuration, and Reconfiguration Timing Diagram and the Using nINIT_DONE to Gate the PLL_Reset Signal diagrams.
  • Added more content to the Agilex™ 5 Configuration Time Estimation section.
  • Added additional information resource for HPS Boot First in the Additional Clock Requirements for HPS and GTS Transceivers section.
2024.07.24 24.2 Updated the text at the following locations to redefine I/O pins in question and the VCCIO_PIO voltage.
  • The Power-On, Configuration, and Reconfiguration Timing Diagram diagram in the Agilex™ 5 Configuration Timing Diagram section.
  • Last bullet point under Power-On in the Configuration Flow Diagram section.
2024.07.08 24.2
  • Added new section Agilex™ 5 Configuration Time Estimation.
  • Added information for supported generic QSPI flash controllers in the Understanding Quad SPI Flash Byte-Addressing section.
  • Added new section CRAM Integrity Check Feature.
2024.04.01 24.1 Initial release.