Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs

ID 813773
Date 7/24/2024
Public
Document Table of Contents

3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration

This section describes the procedures on how to use the Parallel Flash Loader II Intel® FPGA IP.

To target a MAX® II, MAX® V, or MAX® 10 device requires the use of Quartus® Prime Standard Edition software whereas targeting a Agilex™ 5 requires Quartus® Prime Pro Edition software.

The process of creating the Avalon-ST single device configuration design targeting a MAX® II, MAX® V, or MAX® 10 device involves three steps.
  1. Generate the AVST design for the MAX® device with the default option address.
  2. Create the Agilex™ 5 .pof file in setting the appropriate option bits.
  3. Regenerate the Parallel Flash Loader II Intel® FPGA IP with the option bits used to generate the Agilex™ 5 .pof file and recompile the MAX® 10 design.
Figure 29. Process for Using the Parallel Flash Loader II Intel® FPGA IP Figure shows the process for using the Parallel Flash Loader II Intel® FPGA IP, using MAX® II as an example.