Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCs

ID 813762
Date 5/09/2025
Public
Document Table of Contents

6.2.2. HPS IO Hash Handling as related to the HPS EMIF IO Bank(s)

Only the IO banks used by the HPS EMIF IP (those adjacent to the HPS) contribute to the HPS IO hash calculation. To determine which banks are relevant for the HPS IO hash calculation, follow these guidelines.

Table 19.  HPS IO Hash Calculation Guidelines
Device DDR Mode IO Banks

Agilex™ 5

DDR Mode using 2 HPS EMIFs

(ex/ 2x DDR5 x32)

2 IO banks closest to HPS (Banks 3A and 3B)

DDR Mode using 1 HPS EMIF

(ex/ 1x DDR4 x16 + ECC)

1 IO bank closest to HPS (Bank 3A)

Agilex™ 3

DDR Mode using 1 HPS EMIF

(ex/ 1x LPDDRx16 + ECC)

1 IO bank closest to HPS (Bank 3A)

Note: Supports only LPDDR.

Consider the following examples from the Chip Planner and Interface Planner views in Quartus® Prime. The blue box represents the HPS bank, while the red box highlights the two adjacent banks assigned to HPS IO (from HPS EMIF). To achieve an IO hash match, the configuration of these two adjacent IO banks (in the red box in the figure below) must be identical in both project designs.

Figure 43. HPS IO Banks Views

When configuring the IO banks, consider the following factors:

  • Pin assignments for the pins placed in these banks.
  • Cell locations for the cells placed in these banks.
  • Cell parameters for the cells placed in these banks (set through Quartus® Prime IP GUI settings for the parent IPs).
  • Clock usage for the clocks driving to and from these banks.

IPs located in the identified IO banks also affect the HPS IO hash calculation.

The following sections provide more details about each factor that contributes to the hash calculation in HPS IO banks. Additionally, a list of troubleshooting examples for each factor is included at the end of the section.