GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
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4.3. PCIe* Hard IP
The PCIe* Hard IP implements the functionality of the PCIe* protocol. The Hard IP implements Physical, Data Link, and Transaction Layers of the protocol. The Hard IP handles link training, DLLP exchanges, credit handling, BAR decode, and error handling in normal mode. It also implements SR-IOV functionality for virtualization applications.
The Agilex™ 3 FPGAs and SoCs are equipped with PCIe* 3.0 x4 Hard IP, whereas the Agilex™ 5 FPGAs and SoCs offer two distinct variants of PCIe* Hard IP. The performance-optimized D-Series Agilex™ 5 FPGAs feature the PCIe* 4.0 x8 Hard IP, while the power-optimized Agilex™ 5 E-Series FPGAs include the PCIe* 4.0 x4 Hard IP. The Agilex™ 3 devices incorporate the PCIe* 3.0 x4 Hard IP, and the Agilex™ 5 E-Series devices are equipped with the PCIe* 4.0 x4 Hard IP. Both configurations come with a PCIe* x4 controller available in each transceiver bank. In contrast, the PCIe* 4.0 x8 Hard IP in the Agilex™ 5 D-Series devices span two transceiver banks and include both a PCIe* x8 controller and a PCIe* x4 controller. The PCIe* x8 controller can also support a x4 link and hence the PCIe* 4.0 x8 Hard IP in the D-Series devices can be configured to support one or two independent PCIe* x4 links. There are reference clock pins and a System PLL in each transceiver bank, and reset pins in the HVIO banks to support two independent PCIe* x4 link implementations. If only a single PCIe x4 link is required, the PCIe x4 controller is enabled for the implementation. When the PCIe* Hard IP is configured to support PCIe* 4.0 x8 mode with two transceiver banks combined, only the PCIe* x8 controller and the System PLL in the upper bank are active.