1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813667
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP 5. Interface Signals 6. Configuration Registers 7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives 8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the Agilex™ 5 Reference and System PLL IP
3. Functional Description x
3.1. Architecture 3.2. Clocking and Reset Sequence 3.3. Timing Constraints 3.4. Operation Speed Switching 3.5. USXGMII 3.6. Fmax Requirement
3.2. Clocking and Reset Sequence x
3.2.1. Clocking 3.2.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration SRC Signals
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

6.2. PHY Registers

Observe the following guidelines when accessing the registers:
  • Do not write to reserved or undefined registers.
  • When writing to the registers, perform read-modify-write operation to ensure that reserved or undefined register bits are not overwritten.
Table 27.  Types of Register Access
Access Definition
RO Read only.
RW Read and write.
RWC Read, write and clear. The user application writes 1 to the register bit(s) to invoke a defined instruction. The IP core clears the bit(s) upon executing the instruction.
Table 28.  PHY Registers
Address Name Description Access HW Reset Value
0x00 control Bit [15]: RESET. Set this bit to 1 to trigger a soft reset.

The PHY clears the bit when the reset is completed. The register values remain intact during the reset.

 RWC 0
Bit[14]: Reserved — —
Bit [12]: AUTO_NEGOTIATION_ENABLE. Set this bit to 1 to enable auto-negotiation.

Auto-negotiation is supported only in 1GbE. Therefore, set this bit to 0 when you switch to a speed other than 1GbE.

 RW 0
Bit [9]: RESTART_AUTO_NEGOTIATION. Set this bit to 1 to restart auto-negotiation.

The PHY clears the bit as soon as auto-negotiation is restarted.

 RWC 0
All other bits are reserved. — —
0x01 status Bit [5]: AUTO_NEGOTIATION_COMPLETE. A value of "1" indicates that the auto-negotiation is completed. RO 0
Bit [3]: AUTO_NEGOTIATION_ABILITY. A value of "1" indicates that the PCS function supports auto-negotiation. RO 1
Bit [2]: LINK_STATUS. A value of "0" indicates that the link is lost. A value of "1" indicates that the link is established. RO 0
All other bits are reserved. — —
0x02:0x03 phy_identifier The value set in the PHY_IDENTIFIER parameter. RO Value of PHY_IDENTIFIER parameter
0x04 dev_ability Use this register to advertise the device abilities during auto-negotiation. — —
Bits [13:12]: RF. Specify the remote fault.
  • 00: No error.
  • 01: Link failure.
  • 10: Off-line.
  • 11: Auto-negotiation error.
 RW 00
Bits [8:7]: PS. Specify the PAUSE support.
  • 00: No PAUSE.
  • 01: Symmetric PAUSE.
  • 10: Asymmetric PAUSE towards the link partner.
  • 11: Asymmetric and symmetric PAUSE towards the link device.
RW 11
Bit [5]: FD. Ensure that this bit is always set to 1. RW 1
All other bits are reserved. — —
0x05 (1000BASE-X mode) partner_ability The device abilities of the link partner during auto-negotiation. — —
Bit [14]: ACK. A value of "1" indicates that the link partner has received three consecutive matching ability values from the device. RO 0
Bits [13:12]: RF. The remote fault.
  • 00: No error.
  • 01: Link failure.
  • 10: Off-line.
  • 11: Auto-negotiation error.
 RO 0
Bits [8:7]: PS. The PAUSE support.
  • 00: No PAUSE.
  • 01: Symmetric PAUSE.
  • 10: Asymmetric PAUSE towards the link partner.
  • 11: Asymmetric and symmetric PAUSE towards the link device.
 RO 0
Bit [6]: HD. A value of "1" indicates that half-duplex is supported. RO 0
Bit [5]: FD. A value of "1" indicates that full-duplex is supported. RO 0
All other bits are reserved. — —
0x05 (SGMII mode) partner_ability The device abilities of the link partner during auto-negotiation. — —
Bit [11:10]: COPPER_SPEED
Link partner speed:
  • 00: copper interface speed is 10 Mbps
  • 01: copper interface speed is 100 Mbps
  • 10: copper interface speed is 1 Gigabit
  • 11: reserved
 RO 00
Bit [12]: COPPER_DUPLEX_STATUS
Link partner capability:
  • 1: copper interface is capable of full-duplex operation
  • 0: copper interface is capable of half-duplex operation
 RO 0
Bit [14]: ACK. Link partner acknowledge. A value of 1 indicates that the device received three consecutive matching ability values from its link partner. RO 0
Bit [15]: COPPER_LINK_STATUS
Link partner status:
  • 1: copper interface link is up
  • 0: copper interface link is down
 RO 0
All other bits are reserved. — —
0x06 an_expansion The PCS capabilities and auto-negotiation status. — —
Bit [1]: PAGE_RECEIVE. A value of "1" indicates that the partner_ability register has been updated. This bit is automatically cleared once it is read. RO 0
Bit [0]: LINK_PARTNER_AUTO_NEGOTIATION_ABLE. A value of "1" indicates that the link partner supports auto-negotiation. RO 0
0x07 device_next_page The PHY does not support the next page feature. These registers are always set to 0. RO 0
0x08 partner_next_page RO 0
0x0B gmii8b_adapter Transmit data path disable bit. This field disables the transmit data path of the adapter core. It acts as the software reset to all transmit sequential logic in the adapter core (for example the elastic buffer controller).
  • 1: Transmit data path is disabled (default)
  • 0: Transmit data path is enabled
 RW 0x1
0x0C:0x0E Reserved — — —

0x10

 scratch Provides a memory location to test read and write operations.

RW

 0
Bit [31:16]: Reserved — —
0x11 rev The current version of the PHY IP core. RO Current version of the PHY
Bit [31:16]: Reserved — —
0x12:0x13 link_timer 21-bit auto-negotiation link timer. Set the link timer value from 0 to 16 ms in 16 ns steps (62.5 MHz clock periods for 1G). The reset value sets the link timer to ~10 ms (10,002,432 ns).
  • Bit [15:0] are written to word offset 0x12. Bit [8:0] of word offset 0x12 is always set to 0. Any value written to it is ignored.
  • Bit [20:16] are written to word offset 0x13. The remaining bits are reserved and always set to 0. Since bit [8:0] is always set to 0, the highest resolution for 1G is 8192 ns.
RW

[20:9] 0x4C5 [8:0] 0x0

OR

Addr 0x13: [20:16] 0x9 Addr 0x12: [15:0] 0x8A00
0x14 if_mode Interface Mode Register — —
Bit [0]: SGMII_ENA

Determines the PCS function operating mode. Setting this bit to 1b'1 enables SGMII mode. Setting this bit to 1b'0 enables 1000BASE-X gigabit mode.

RW 0
Bit [1]: USE_SGMII_AN

In SGMII mode, setting this bit to 1b'1 configures the PCS with the link partner abilities advertised during auto-negotiation. If this bit is set to 1b'0, the PCS function should be configured with the SGMII_SPEED bits.

RW 0
Bit [3:2]: SGMII_SPEED
When the PCS operates in SGMII mode (SGMII_ENA = 1) and is not programmed for automatic configuration (USE_SGMII_AN = 0), the following encodings specify the speed:
  • 2'b00: 10 Mbps
  • 2'b01: 100 Mbps
  • 2'b10: Gigabit
  • 2'b11: Reserved
These bits are not used when SGMII_ENA = 0 or USE_SGMII_AN = 1.
RW 0
All other bits are reserved. — —
0x15 Reserved — — —
0x17 dl_ctrl Bit [0]: tx_measure_valid
Indicates whether the TX deterministic latency measurement values are valid
  • 0: Not valid
  • 1: Valid
 RO 0x0
Bit [1]: rx_measure_valid
Indicates whether the RX deterministic latency measurement values are valid.
  • 0: Not valid
  • 1: Valid
 RO 0x0
Bit [2]: tx_dl_reset
TX Deterministic Latency (DL) soft reset. Provides a soft reset to the TX DL block.
  • 0: TX DL block is not under reset
  • 1: TX DL block is being reset
Note: This is not a self-clearing reset.
RW 0x0
Bit [3]: rx_dl_reset
RX Deterministic Latency (DL) soft reset. Provides a soft reset to the RX DL block.
  • 0: RX DL block is not under reset
  • 1: RX DL block is being reset
Note: This is not a self-clearing reset.
RW 0x0
0x19:0x18 tx_delay Bit [20:0]: TX Datapath Latency.
Provides the TX datapath deterministic latency values measured in i_dl_sampling_clk cycles.
  • 0x18:
    • Bit [15:8]: Unused.
    • Bit [7:0]: The fractional number of clock cycles.
  • 0x19:
    • Bit [15:13]: Unused.
    • Bit [12:0]: The number of clock cycles.

You must set the measure_valid before taking the measurement.

RO 0x0
0x1B:0x1A rx_delay Bit [20:0]: RX Datapath Latency.
Provides the RX datapath deterministic latency values measured in i_dl_sampling_clk cycles.
  • 0x1A:
    • Bit [15:8]: Unused.
    • Bit [7:0]: The fractional number of clock cycles.
  • 0x1B:
    • Bit [15:13]: Unused.
    • Bit [12:0]: The number of clock cycles.

You must set the measure_valid before taking the measurement.

RO 0x0
0x1D:0x1C tx_soft_pcs_latency Bit [21:0]: TX Soft PCS Datapath Latency.
Provides the latency values measured from GMII input interface to 20-bit parallel output of soft PCS logic.
Note: The value of gmii16b_tx_latency can be read from this register.
  • 0x1C:
    • Bit [15:10]: Unused.
    • Bit [9:0]: The fractional number of clock cycles.
  • 0x1D:
    • Bit [15:12]: Unused.
    • Bit [11:0]: The number of clock cycles.
 RO 0x0
0x1F:0x1E rx_soft_pcs_latency Bit [21:0]: RX Soft PCS Datapath Latency.
Provides the latency values measured from 20-bit parallel output of soft PCS logic to GMII output interface of PHY IP..
Note: The value of gmii16b_rx_latency can be read from this register.
  • 0x1E:
    • Bit [15:10]: Unused.
    • Bit [9:0]: The fractional number of clock cycles.
  • 0x1F:
    • Bit [15:12]: Unused.
    • Bit [11:0]: The number of clock cycles.
 RO 0x0
0x400 usxgmii_control Control Register — —
Bit [0]: USXGMII_ENA:
  • 0: None
  • 1: USXGMII mode
 RW 0
Bit [1]: USXGMII_AN_ENA is used when USXGMII_ENA is set to 1:
  • 0: Disables USXGMII Auto-Negotiation and manually configures the operating speed with the USXGMII_SPEED register.
  • 1: Enables USXGMII Auto-Negotiation, and automatically configures operating speed with link partner ability advertised during USXGMII Auto-Negotiation.
RW 1
Bit [4:2]: USXGMII_SPEED is the operating speed of the PHY in USXGMII mode and USE_USXGMII_AN is set to 0.
  • 3’b000: 10M
  • 3’b001: 100M
  • 3’b010: 1G
  • 3’b011: 10G
  • 3’b100: 2.5G
  • 3’b101: 5G
  • 3’b110: Reserved
  • 3’b111: Reserved
 RW 0
Bit [8:5]: Reserved — —
Bit [9]: RESTART_AUTO_NEGOTIATION

Write 1 to restart Auto-Negotiation sequence. The bit is cleared by hardware when Auto-Negotiation is restarted.

 RWC 0
Bit [31:10]: Reserved — —
0x401 usxgmii_status Status Register — —
Bit [1:0]: Reserved — —
Bit [2]: LINK_STATUS indicates link status for USXGMII all speeds
  • 1: Link is established
  • 0: Link synchronization is lost, a 0 is latched
 RO 0
Bit [4:3]: Reserved — —
Bit [5]: AUTO_NEGOTIATION_COMPLETE

A value of 1 indicates the Auto-Negotiation process is completed.

 RO 0
Bit [31:6]: Reserved — —
0x402:0x404 Reserved — — —
0x405 usxgmii_partner_ability Device abilities advertised to the link partner during Auto-Negotiation. — —
Bit [6:0]: Reserved — —
Bit [7]: EEE_CLOCK_STOP_CAPABILITY
Indicates whether energy efficient Ethernet (EEE) clock stop is supported.
  • 0: Not supported
  • 1: Supported
 RO 0
Bit [8]: EEE_CAPABILITY
Indicates whether EEE is supported.
  • 0: Not supported
  • 1: Supported
 RO 0
Bit [11:9]: SPEED
  • 3'b000: 10M
  • 3'b001: 100M
  • 3'b010: 1G
  • 3'b011: 10G
  • 3'b100: 2.5G
  • 3'b101: 5G
  • 3'b110: Reserved
  • 3'b111: Reserved
 RO 0
Bit [12]: DUPLEX
Indicates the duplex mode.
  • 0: Half duplex
  • 1: Full duplex
 RO 0
Bit [13]: Reserved — —
Bit [14]: ACKNOWLEDGE

A value of 1 indicates that the device has received three consecutive matching ability values from its link partner.

 RO 0
Bit [15]: LINK
Indicates the link status.
  • 0: Link down
  • 1: Link up
 RO 0
Bit [31:16]: Reserved — —
0x406:0x411 Reserved — — —
0x412 usxgmii_link_timer

Auto-Negotiation link timer. Sets the link timer value in bit [19:14] from 0 to 2 ms in approximately 0.05-ms steps. You must program the link timer to ensure that it matches the link timer value of the external NBASE-T PHY IP Core.

The reset value sets the link timer to approximately 1.6 ms.

Bits [13:0] are reserved and always set to 0.

 [19:14]: RW

[13:0]: RO

 [19:14]: 1F

[13:0]: 0
0x413:0x41F Reserved — — —
0x420 ptp_dl Bit [0]: tx_measure_valid
Indicates whether the TX deterministic latency measurement values are valid.
  • 0: Not valid
  • 1: Valid
 RO 0x0
Bit [1]: rx_measure_valid
Indicates whether the RX deterministic latency measurement values are valid.
  • 0: Not valid
  • 1: Valid
Bit [2]: tx_dl_reset
TX Deterministic Latency (DL) soft reset. Provides a soft reset to the TX DL block.
  • 0: TX DL block is not under reset
  • 1: TX DL block is being reset
Note: This is not a self-clearing reset.
Bit [3]: rx_dl_reset

RX Deterministic Latency (DL) soft reset. Provides a soft reset to the RX DL block.

  • 0: RX DL block is not under reset
  • 1: RX DL block is being reset
Note: This is not a self-clearing reset.
0x421 ptp_dl_tx Bit [20:0]: TX Datapath Latency.
Provides the TX datapath deterministic latency values measured in sampling_clk cycles. Fixed point format Q13.8.
  • Bit [20:8]: The number of clock cycles.
  • Bit [7:0]: The fractional number of clock cycles.

tx_measure_valid (bit 0 of register 0x420) must be asserted before taking the measurement.

RO 0x0
0x422 ptp_dl_rx Bit [20:0]: RX Datapath Latency.
Provides the RX datapath deterministic latency values measured in sampling_clk cycles. Fixed point format Q13.8.
  • Bit [20:8]: The number of clock cycles.
  • Bit [7:0]: The fractional number of clock cycles.

rx_measure_valid (bit 0 of register 0x420) must be asserted before taking the measurement.

RO 0x0
0x461 phy_serial_loopback Configures the transceiver serial loopback in the PMA from TX to RX.
  • Bit [0]:
    • 0: Disables the PHY serial loopback.
    • 1: Enables the PHY serial loopack.
  • Bit [31:1]: Reserved
 RW 0
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