Low Latency Ethernet 10G MAC IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

ID 813665
Date 8/04/2025
Public
Document Table of Contents

7.5.1. Test Procedure

Follow these steps to test the design examples in hardware:

  1. Click Tools > System Debugging Tools > System Console or run command: system-console &.
  2. Navigate to the hardware design directory: cd <design_example>/LL10G_2_5G_SM_1588v2/hwtesting/system_console.
  3. Run the following command in the System Console:
    1. source main.tcl
    2. set_jtag <select_appropriate_jtag_master>
    Note: The set_jtag command places the Agilex™ 5 device on the JTAG chain.
  4. Run the following commands in the system console to start the test:

    TEST_EXT_LB <from_channel> <to_channel> <speed>

    Example: TEST_1588 0 0 2.5G

    Note: You must connect the external QSFP28 loopback module to bank 1A before running the test.
    Table 21.  Command Parameters
    Parameter Valid Values Description
    channel 0, 1 The channel number to test.
    speed 2.5G The PHY speed.
    Note:
    1. You must connect the external QSFP28 loopback module to the desired QSFP1 port before running the test.
    2. Two channels are supported—channel 0 and channel 1.
  5. The following sample output illustrate a successful hardware test run:
    Figure 43. Sample Test Output