Low Latency Ethernet 10G MAC IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813665
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10M/100M/1G/2.5G Ethernet Design Example 3. 10M/100M/1G/2.5G/10G Ethernet Design Example 4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature 5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature 6. 2.5G Ethernet Design Example 7. 2.5G Ethernet Design Example with IEEE 1588v2 Feature 8. 10M/100M/1G/2.5G/10G MGE (Multi Gigabit Ethernet) PCS Only Ethernet Design Example 9. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 10. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588v2 Feature 11. Interface Signals Description 12. Configuration Registers Description 13. Low Latency Ethernet 10G MAC IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 14. Document Revision History for the Low Latency Ethernet 10G MAC IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Signal Tap Debugging
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Procedure 1.4.2. Hardware Setup
1.5. Signal Tap Debugging x
1.5.1. Signals Description 1.5.2. Signals List
2. 10M/100M/1G/2.5G Ethernet Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme 2.3.3. Reset Scheme
2.5. Hardware Testing x
2.5.1. Test Procedure
3. 10M/100M/1G/2.5G/10G Ethernet Design Example x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.5. Hardware Testing x
3.5.1. Test Procedure
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Interface Signals 4.7. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking Scheme 4.3.3. Reset Scheme
4.4. Simulation x
4.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
4.5. Hardware Testing x
4.5.1. Test Procedure
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Interface Signals 5.7. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme
5.4. Simulation x
5.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
5.5. Hardware Testing x
5.5.1. Test Procedure
6. 2.5G Ethernet Design Example x
6.1. Features 6.2. Hardware and Software Requirements 6.3. Functional Description 6.4. Simulation 6.5. Hardware Testing 6.6. Interface Signals 6.7. Configuration Registers
6.3. Functional Description x
6.3.1. Design Components 6.3.2. Clocking Scheme 6.3.3. Reset Scheme
6.5. Hardware Testing x
6.5.1. Test Procedure
7. 2.5G Ethernet Design Example with IEEE 1588v2 Feature x
7.1. Features 7.2. Hardware and Software Requirements 7.3. Functional Description 7.4. Simulation 7.5. Hardware Testing 7.6. Interface Signals 7.7. Configuration Registers
7.3. Functional Description x
7.3.1. Design Components 7.3.2. Clocking Scheme 7.3.3. Reset Scheme
7.4. Simulation x
7.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
7.5. Hardware Testing x
7.5.1. Test Procedure
8. 10M/100M/1G/2.5G/10G MGE (Multi Gigabit Ethernet) PCS Only Ethernet Design Example x
8.1. Features 8.2. Hardware and Software Requirements 8.3. Functional Description 8.4. Simulation 8.5. Hardware Testing 8.6. Interface Signals 8.7. Configuration Registers
8.3. Functional Description x
8.3.1. Design Components 8.3.2. Clocking Scheme 8.3.3. Reset Scheme
8.5. Hardware Testing x
8.5.1. Test Procedure
9. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
9.1. Features 9.2. Hardware and Software Requirements 9.3. Functional Description 9.4. Simulation 9.5. Hardware Testing 9.6. Interface Signals 9.7. Configuration Registers
9.3. Functional Description x
9.3.1. Design Components 9.3.2. Clocking Scheme 9.3.3. Reset Scheme
9.5. Hardware Testing x
9.5.1. Test Procedure
10. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588v2 Feature x
10.1. Features 10.2. Hardware and Software Requirements 10.3. Functional Description 10.4. Simulation 10.5. Hardware Testing 10.6. Interface Signals
10.3. Functional Description x
10.3.1. Design Components 10.3.2. Clocking Scheme 10.3.3. Reset Scheme
10.4. Simulation x
10.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
10.5. Hardware Testing x
10.5.1. Test Procedure
11. Interface Signals Description x
11.1. Clock and Reset Interface Signals 11.2. Avalon® Memory-Mapped Interface Signals 11.3. Avalon® Streaming Interface Signals 11.4. PHY Interface Signals 11.5. Status Interface 11.6. IEEE 1588v2 Timestamp Interface Signals
12. Configuration Registers Description x
12.1. Register Access Definition 12.2. Low Latency Ethernet 10G MAC 12.3. PHY 12.4. Packet Generator and Traffic Monitor Register Map
12.3. PHY x
12.3.1. 1G/2.5G/5G/10G Multirate PHY
1. Quick Start Guide
2. 10M/100M/1G/2.5G Ethernet Design Example
3. 10M/100M/1G/2.5G/10G Ethernet Design Example
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
6. 2.5G Ethernet Design Example
7. 2.5G Ethernet Design Example with IEEE 1588v2 Feature
8. 10M/100M/1G/2.5G/10G MGE (Multi Gigabit Ethernet) PCS Only Ethernet Design Example
9. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
10. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588v2 Feature
11. Interface Signals Description
12. Configuration Registers Description
13. Low Latency Ethernet 10G MAC IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
14. Document Revision History for the Low Latency Ethernet 10G MAC IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

11.2. Avalon® Memory-Mapped Interface Signals

Table 33.   Avalon® Memory-Mapped Interface Signals
Signal Direction Description

csr_mch_write

 In Assert this signal to request a write to Avalon® memory-mapped address decoder.

csr_mch_read

 In Assert this signal to request a read to Avalon® memory-mapped address decoder.
csr_mch_address In Use this bus to specify the register address you want to read from or write to.

csr_mch_writedata

 In Carries the data to be written to the specified register.

csr_mch_readdata

 Out Carries the data read from the specified register.

csr_mch_waitrequest

 Out When asserted, this signal indicates that the IP is busy and not ready to accept any read or write requests.

csr_mac_write

 In Assert this signal to request a write to MAC IP.

csr_mac_read

 In Assert this signal to request a read to MAC IP.
csr_mac_address In Use this bus to specify the register address you want to read from or write to.

csr_mac_writedata

 In Carries the data to be written to the specified register.

csr_mac_readdata

 Out Carries the data read from the specified register.

csr_mac_waitrequest

 Out When asserted, this signal indicates that the IP is busy and not ready to accept any read or write requests.

csr_phy_write

 In Assert this signal to request a write to 1G/2.5G/5G/10G Multirate Ethernet PHY IP.

csr_phy_read

 In Assert this signal to request a read to 1G/2.5G/5G/10G Multirate Ethernet PHY IP.
csr_phy_address In Use this bus to specify the register address you want to read from or write to.

csr_phy_writedata

 In Carries the data to be written to the specified register.

csr_phy_readdata

 Out Carries the data read from the specified register.

csr_phy_waitrequest

 Out When asserted, this signal indicates that the IP is busy and not ready to accept any read or write requests.
csr_dphy_rcfg_address   Use this bus to specify the register address you want to read from or write to.

csr_dphy_rcfg_write

 In Assert this signal to request a write to Direct PHY IP.

csr_dphy_rcfg_read

 In Assert this signal to request a read to Direct PHY IP.

csr_dphy_rcfg_writedata

 In Carries the data to be written to the specified register.

csr_dphy_rcfg_readdatavalid

 Out When asserted, this signal indicates that the read data is valid.

csr_dphy_rcfg_readdata

 Out Carries the data read from the specified register.

csr_dphy_rcfg_waitrequest

 Out When asserted, this signal indicates that the IP is busy and not ready to accept any read or write requests.
i_dr_avmm_address   Use this bus to specify the register address you want to read from or write to.

o_dr_avmm_readdatavalid

 Out When asserted, this signal indicates that the read data is valid.

i_dr_avmm_read

 In Assert this signal to request a read to Dynamic Reconfiguration IP.

o_dr_avmm_readdata

 Out Carries the data read from the specified register.

i_dr_avmm_writedata

 In Carries the data to be written to the specified register.

i_dr_avmm_write

 In Assert this signal to request a write to Direct PHY IP.

o_dr_avmm_waitrequest

 Out When asserted, this signal indicates that the IP is busy and not ready to accept any read or write requests.
Level Two Title