Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
ID
813665
Date
10/07/2024
Public
A newer version of this document is available. Customers should click here to go to the newest version.
1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 2.5G Ethernet Design Example with IEEE 1588v2 Feature
6. 10G Ethernet Design Example
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
8. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
9. Interface Signals Description
10. Configuration Registers Description
11. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
12. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1.3.2. Testbench
Figure 4. Block Diagram of the Testbench
Component | Description |
---|---|
Device under test (DUT) | The design example. |
Avalon® driver | Consists of Avalon® streaming master bus functional models (BFMs). This driver forms the TX and RX paths. The driver also provides access to the Avalon® memory-mapped interface of the DUT. |
Ethernet packet monitors | Monitor TX and RX datapaths, and display the frames in the simulator console. |