Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813665
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10M/100M/1G Ethernet Design Example 3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature 4. 2.5G Ethernet Design Example 5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 6. Interface Signals Description 7. Configuration Registers Description 8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling the Design Example
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
2. 10M/100M/1G Ethernet Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Interface Signals 2.6. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme 2.3.3. Reset Scheme
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Interface Signals 3.6. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Interface Signals 4.6. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking Scheme 4.3.3. Reset Scheme
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Interface Signals 5.6. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme
6. Interface Signals Description x
6.1. Clock and Reset Interface Signals 6.2. Avalon® Memory-Mapped Interface Signals 6.3. Avalon® Streaming Interface Signals 6.4. PHY Interface Signals 6.5. Status Interface 6.6. IEEE 1588v2 Timestamp Interface Signals
7. Configuration Registers Description x
7.1. Register Access Definition 7.2. Low Latency Ethernet 10G MAC 7.3. PHY
7.3. PHY x
7.3.1. 1G/2.5G/5G/10G Multirate PHY
1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. Interface Signals Description
7. Configuration Registers Description
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5

3.3.1. Design Components

Table 6.  Design Components
Component Description
LL 10GbE MAC

The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:

  • Speed: 1G/2.5G
  • Datapath options: TX & RX
  • Enable ECC on memory blocks: Not selected
  • Enable preamble pass-through mode: Not selected
  • Enable priority-based flow control (PFC): Not selected
  • Enable supplementary address: Selected
  • Enable statistics collection: Selected
  • Statistics counters: Memory-based
  • TX and RX datapath Reset/Default To Enable: Selected
  • Enable time stamping: Selected
  • Enable PTP one-step clock support: Selected
  • Enable asymmetry support: Not selected
  • Enable peer-to-peer support: Not selected
  • Timestamp fingerprint width: 4
  • Time of Day format: Enable both 96b and 64b Time of Day Format
PHY The 1G/2.5G Multirate Ethernet PHY Intel® FPGA IP with the following configuration:
  • Connect to MGBASE-T PHY: Selected
  • Connect to NBASE-T PHY: Not selected
  • Speed: 1G/2.5G
  • Enable SGMII bridge: Not selected
  • Enabled IEEE 1588 Precision Time Protocol: Selected
  • Enable GMII Adapter: Not selected
  • PHY ID (32 bit): 0x00000000
  • Default Mode: 1 GbE
  • PMA Reference Frequency: 156.25 MHz
  • syspll_outclk_freq_mhz: 322.265 MHz
GTS Reset Sequencer Resets the transceiver.
Address Decoder Decodes the addresses of the components.
System PLL Supports system PLL clocking mode for Direct PHY.
Design Components for the IEEE 1588v2 Feature
Time of Day Clock The TOD for each channel.
TOD Synchronizer Synchronizes the master TOD to all local TODs.
Ethernet Packet Classifier Decodes the packet type of incoming PTP packets and returns the decoded information to the Low Latency Ethernet 10G MAC Intel® FPGA IP.
Level Two Title