Cyclone® V to Agilex™ 5 Device Migration Guide

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ID 787947
Date 9/30/2024
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

2.5. Logic Elements and Embedded Memory

Agilex™ 5 embedded memory blocks are flexible and provide an optimal amount of various-sized memory arrays to fit your design requirements. Unlike Cyclone® V devices, Agilex™ 5 devices offer the 20 Kb M20K-blocks-dedicated memory resources to support larger memory array designs while providing many independent ports. However, a direct migration might not be possible due to significant feature difference. Intel recommends using a new IP in the Agilex™ 5 device to fully utilize the latest features in embedded memory blocks.

The following table lists key differences between Cyclone® V and Agilex™ 5 devices for embedded memory migration:

Table 9.  Key Feature Differences for Embedded Memory Migration
Features Cyclone® V Agilex™ 5
Memory block type

M10K

MLAB

M20K

MLAB
Byte-enable support Supported Supported
Address clock enable (address stall) Supported Supported
Simple dual-port mixed width Supported Supported
FIFO buffer mixed width Supported Supported
Memory Initialization File (.mif) Supported Supported
Dual-clock mode Not Supported Supported
Full synchronous memory Supported Restricted
Asynchronous memory Restricted Restricted
Power-up state Supported Supported
Asynchronous clears Supported Supported
Synchronous clears Not Supported Supported
Write/read operation triggering Supported Supported
Same-port read-during-write Supported Supported
Mixed-port read-during-write Supported Supported
Error Correction Code (ECC) support Supported Supported
Force-to-zero Not Supported Supported
Coherent read memory Not Supported Supported
Freeze logic Not Supported Supported
True Dual Port (TDP) dual clock emulator Not Supported Supported

Agilex™ 5 device offers increased total RAM bits ideal for larger memory arrays and more features support. In terms of Quartus® Prime IPs, you cannot directly migrate the on-chip memory IPs from Cyclone® V to Agilex™ 5 devices. You must reinstantiate the on-chip memory IP.

The following table summarizes aspects of Agilex™ 5 programmable logic core fabric compared to Cyclone® V:

Table 10.   Cyclone® V and Agilex™ 5 Programmable Logic Core Fabric Comparison
Feature Cyclone® V Agilex™ 5
Logic Array Block (LAB) to Memory Logic Array Block (MLAB) ratio 1:3 1:1
Logic architecture

Adaptive Logic Module (ALM): Fracturable 6LUT + 4FF

ALM: Fracturable 6LUT + 4FF
LAB capacity 10 ALM 10 ALM
Logic RAM LUTRAM supporting 32x2 bits per ALM LUTRAM supporting 32x2 bits per ALM
HyperFlex Not supported Supported
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