Intel® Simics® Simulator for Intel® FPGAs: Intel Agilex® 5 E-Series Virtual Platform User Guide

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ID 786901
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About This Document 2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms 3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model 5. Supported Use Cases A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms x
2.1. Intel Agilex® 5 E-Series Universal Virtual Platform
2.1. Intel Agilex® 5 E-Series Universal Virtual Platform x
2.1.1. Intel Agilex® 5 E-Series Universal Virtual Platform Overview 2.1.2. Intel Agilex® 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.1.3. Intel Agilex® 5 E-Series Virtual Platform Key Capabilities
2.1.1. Intel Agilex® 5 E-Series Universal Virtual Platform Overview x
2.1.1.1. Intel Agilex® 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Intel Agilex® 5 E-Series Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges
3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components
3.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model x
3.1.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Intel Agilex® 5 E-Series HPS Components
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Intel Agilex® 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platforms
3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model
5. Supported Use Cases
A. Document Revision History

3.1.3. MPU and APS Subsystem

The following table lists the support status for components integrated into the MPU and APS subsystems. The table also indicates any component limitations and the object created under the HPS Intel® Simics® model of the Intel Agilex® 5 E-Series HPS.

Table 7.   Component Support Status | Limitations | Objects
Component Supported? Limitations | Objects
MPU Sub-System Yes
  • Limitations:
    • The A76 core model is based on the r3p0 version while the real hardware uses r4p1 version.
    • Cache memories are not modeled. Intel® Simics® implements the parts visible to the software in the path towards the cache, but the real functionality is not implemented, so there is no information on hits/misses or cache operations, such as cache flushes.
  • Objects:
    • A55: system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0]
    • A55: system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[1]
    • A76: system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[2]
    • A76: system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[3]
    • DSU: system.board.fpga.soc_inst.hps_subsys.agilex_hps.dsu
CoreSight Debug and Trace No N/A
Interrupt Controller Yes Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.gic
Cache Coherency Unit (CCU) Yes
  • Limitation: This is just a skeleton model with read/write access to registers.
  • Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.ccu
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