Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide

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ID 776646
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with the Default Factory Image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. BTS Functionalities 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The FMCA NRZ Tab 4.2.5.3. The FMCB NRZ Tab 4.2.5.4. The QSFPDD400/QSFPDD800 PAM4 Tab 4.2.5.5. The QSFP NRZ Tab 4.2.5.6. The SFP Tab 4.2.5.7. The OSFP Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.2. Configuring the FPGA Device by Avalon® Streaming Modes
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Communication Interfaces A.8. Daughter Cards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.5. General Input/Output

Table 9.   MAX® 10 and FPGA
Schematic Signal Name Description
F_GPIO0 The value of the filtered user_pb[0].​
F_GPIO1 The value of the filtered user_pb[1]​.
F_GPIO2 Reserved​
F_GPIO3 Reserved​
F_GPIO4 Reserved​
F_GPIO5 Reserved​
F_GPIO6 Reserved​
F_GPIO7 ​Reserved
F_GPIO8 ​Reserved
F_GPIO9 ​Reserved
F_GPIO10 ​Used for DIP Switch
F_GPIO11 ​Used for Switch Data Transfer
Table 10.  System MAX® 10
Schematic Signal Name Description
USER_PB0 User Push Button
USER_PB1 User Push Button
USER_SW0 User Switch
USER_SW1 User Switch
USER_SW2 User Switch
USER_SW3 User Switch
USER_SW4 User Switch
USER_SW5 User Switch
USER_SW6 User Switch
USER_SW7 User Switch
SYS_PWR_RSV3 Reserved GPIO between system MAX® 10 and Power MAX® 10
SYS_PWR_RSV2 Reserved GPIO between system MAX® 10 and Power MAX® 10
SYS_PWR_RSV1 Reserved GPIO between system MAX® 10 and Power MAX® 10
SYS_PWR_RSV0 Reserved GPIO between system MAX® 10 and Power MAX® 10
USER_LED0 User LED
USER_LED1 User LED
USER_LED2 User LED
USER_LED3 User LED
USER_LED4 User LED
USER_LED5 User LED
USER_LED6 User LED
USER_LED7 User LED
F_GPIO0 The value of the filtered user_pb[0]​
F_GPIO1 The value of the filtered user_pb[1]​
F_GPIO2 MCIO_PERST in RP mode​
F_GPIO3 FMC_A_PERST in RP mode​
F_GPIO4 FMC_B_PERST in RP mode​
F_GPIO5 Reserved​
F_GPIO6 ​Reserved
F_GPIO7 ​Reserved
F_GPIO8 ​Reserved
F_GPIO9 ​Reserved
F_GPIO10 ​Reserved
F_GPIO11 ​Reserved
SYS_SW0​

Factory load:

0—Load image from Page 0 of the QSPI

SYS_SW1​ NU ​
SYS_SW2​ ​NU
SYS_SW3​ ​NU
SYS_SW4​ ​NU
SYS_SW5​

FMC-A PCIe* RP/EP Select:​

"0": RP​

"1": EP​
SYS_SW6​

FMC-B PCIe* RP/EP Select:​

"0": RP​

"1": EP​
SYS_SW7​

MCIO PCIe* RP/EP Select:​

"0": RP​

"1": EP​
SYS_LED0/D9​ PGM_LED0 for Avalon® streaming configuration​
SYS_LED2/D11​ PGM_LED1 for Avalon® streaming configuration​
SYS_LED4/D13​ PGM_LED2 for Avalon® streaming configuration​
SYS_LED6/D15​ MAX_ERROR for Avalon® streaming configuration​
SYS_LED1/D10​ MAX_LOAD for Avalon® streaming configuration​
SYS_LED3/D12​ MAX_CONF_DONE for Avalon® streaming configuration​
SYS_LED5/D14​ Reserved​
SYS_LED7/D16​ Reserved​
SYS_PB0/S11​ MAX_RESETn​
SYS_PB1/S12​ FPGA_RESETn​
SYS_PB2/S14​ Power recycle​
SYS_PB3/S16​ PGM_SEL for Avalon® streaming configuration​
SYS_PB4/S17​ PGM_CFG for Avalon® streaming configuration​
FPGA_FAN_PWM Fan 2 PWM signal
FPGA_FAN_TACH Fan 2 tachometer signal
QSFP_RIGHT_FAN_PWM Fan 3 PWM signal
QSFP_RIGHT_FAN_TACH Fan 3 tachometer signal
QSFP_LEFT_FAN_PWM Fan 1 PWM signal
QSFP_LEFT_FAN_TACH Fan 1 tachometer signal
CORE_FETS_FAN_PWM Fan 0 PWM signal
CORE_FETS_FAN_TACH Fan 0 tachometer signal
MUX_SEL0 Mux Select for choosing either REFCLK_FGT_12A_8_DP/N (or) REFCLK_FGT_12A_9_DP/N for FMCA_RECRD_CLK 0: FMCA_RECRD_CLK= REFCLK_FGT_12A_8_DP/N 1: FMCA_RECRD_CLK= REFCLK_FGT_12A_9_DP/N
MUX_SEL1 Mux select for choosing either REFCLK_FGT_13C_8_DP/N (or) REFCLK_FGT_13C_9_DP/N for FMCB_RECRD_CLK 0: FMCA_RECRD_CLK= REFCLK_FGT_13C_8_DP/N 1: FMCA_RECRD_CLK= REFCLK_FGT_13C_9_DP/N
MCIO_CLK_SEL_EP_N Tied to MUX_DIP_SW2
MCIO_CLK_ENN Tied to MUX_DIP_SW3
MUX_DIP_SW0 DIP switch 0 signal (high by default)—tie this to MUX_SEL0
MUX_DIP_SW1 DIP switch 1 signal (high by default)—tie this to MUX_SEL1
MUX_DIP_SW2 MCIO_CLK_SEL_EP_NN:

Low before system power OK

High after system power OK
MUX_DIP_SW3 MCIO_CLK_ENN:

High before system power OK

Low after system power OK
VCCL_I2C_EN Connect VCCL_SCL/SDA to system MAX® 10 (Default: ENABLE-1)
R_13C_PERST_IO_N Driven low
R_13B_PERST_IO_N Tied to MCIO PREST internally
R_12B_PERST_IO_N Driven low
R_12C_PERST_IO_N Driven low
SI5395_1_A_IN_SEL0_R Do not use (DNU)
SI5395_2_A_OEN_SYS_R

High before system power OK

Low after system power OK
SI52204_PWRGD_R Tied to system power OK
SI5395_2_A_IN_SEL0_R DNU
SI5395_1_A_OEN_SYS_R

High before system power OK

Low after system power OK
SI5391_A_OEN

High before system power OK

Low after system power OK
SI5391_A_RSTN

Low until system power OK

High after system power OK
SI5518_GPIO_0_R DNU
CLK_OE_0_N

SI52204 CLK ENABLE0:

High before system power OK

Low after system power OK
CLK_OE_1_N

SI52204 CLK ENABLE1:

High before system power OK

Low after system power OK
CLK_OE_2_N

SI52204 CLK ENABLE2:

High before system power OK

Low after system power OK
SI5518_GPIO_1_R DNU
SI5518_GPIO_2_R DNU
CLK_SI5395_2_FINC_R DNU
CLK_SI5395_2_FDEC_R DNU
CLK_SI5395_1_FINC_R DNU
CLK_SI5395_1_FDEC_R DNU
SI5518_I2C_R_EN

Keep it enabled:

Low before system power OK

DNU after system power OK
R_12A_SPARE_N Driven low
R_13A_SPARE_N Driven low
DIMM_IO_R_EN

Enable always after system power OK

Low before system power OK

DNU after system power OK
FMC_B_PCIE_PERSTN_3V3 DNU
FMC_B_PCIE_WAKEN_3V3 DNU
FMC_A_PCIE_WAKEN_3V3 DNU
FMC_A_PCIE_PERSTN_3V3 DNU
Table 11.  UB2/PWR MAX® 10
Schematic Signal Name Description
FPGA_POK_LED FPGA Power Good
SYS_PWR_RSV0 Reserved GPIO between system MAX® 10 and power MAX® 10
SYS_PWR_RSV1 Reserved GPIO between system MAX® 10 and power MAX® 10
SYS_PWR_RSV2 Reserved GPIO between system MAX® 10 and power MAX® 10
SYS_PWR_RSV3 Reserved GPIO between system MAX® 10 and ower MAX® 10
PWR_PB0 POWER MAX PB0—FU
Level Two Title