3.3. Top-Level Signals of the HBM2E Design Example
|Signal Group||Signal Name||Direction||Width||Description|
|Clocks||core_pll_refclk_clk||Input||1||LVDS differential reference clock used by the I/O PLL to generate the fabric core clock. The design example automatically instantiates the I/O PLL that generates the core clock.|
|uibpll_refclk_clk||Input||1||LVDS differential reference clock used by the UIB PLL. The design example automatically instantiates the UIB PLL that generates the clock for the UIB subsystem.|
Single-ended reference clock used by the NoC PLL to generate the NoC clock. The design example automatically instantiates a NoC Clock Control block that contains the NoC PLL.
|Resets||global_user_reset_reset_n||Input||1||Active-low asynchronous reset for the entire design example, including the UIB subsystem. When you make a pin assignment for this input, design rule checks may indicate that an input delay assignment is required. You can safely ignore these DRC warnings because the reset is fully asynchronous.|
|hbm_only_reset_reset||Input||1||Active-high asynchronous reset for the HBM2E subsystem only. If you selected the Reset with Calibration reset type during HBM2E IP configuration, the HBM2E memory interface is calibrated. If you do not need to separately reset the HBM2E subsystem, you can tie this input low.|
|Special Signals for use by the Intel® Quartus® Prime software.||hbm_cattrip_vitual_i_conduit||Input||1||Special signal for internal use by the Intel® Quartus® Prime software. You cannot use this signal in any way, and it must be exported by the top level of your design.|
|hbm_temp _vitual_i_conduit||Input||3||Special signal for internal use by the Intel® Quartus® Prime software. You cannot use this signal in any way, and it must be exported by the top level of your design.|
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