External Memory Interfaces Agilex™ 7 M-Series FPGA IP Core Release Notes

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Date 9/29/2025
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1. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Release Notes
1. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Release Notes x
1.1. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v4.1.0 1.2. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v4.0.0 1.3. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v3.0.0 1.4. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v2.0.0 1.5. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v1.0.0 1.6. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v6.2.0 1.7. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v6.1.0 1.8. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v6.0.0 1.9. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP v5.0.0 1.10. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP v4.0.0 1.11. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP v3.0.0
1. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Release Notes

1.1. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v4.1.0

Table 1.  v4.1.0 2025.09.29
Description Impact
Verified in the Quartus® Prime software v25.3. Provides external memory interface IPs for DDR4 Component, DDR4 DIMM, DDR5 Component, DDR5 DIMM, and LPDDR5, for Agilex™ 7 M-Series devices. The tables that follow summarize speed and feature support.
Requirement when migrating from a previous version to v25.3.

To port your previous Agilex™ 7 M-Series EMIF design to the Quartus® Prime software v25.3, you must manually update some parameters or assignments, as discussed below.

Migrating NoC Design

Migrating an EMIF design using NoC from v25.1.1 to v25.3 may cause the error: No NoC connection found for target atoms, due to a change in the NoC Target hierarchy path.

You must update your NoC assignments to match the new hierarchy. For example:

Old Hierarchy

set_instance_assignment -name NOC_READ_BANDWIDTH 6.4 -from noc_init|intel_noc_initiator_inst|iniu_0|initiator_inst_0 -to emif_io96b_ddr5comp_0|emif_io96b_ddr5comp_inst|t0.tniu_0|tniu_0|target_0.target_inst_0

New Hierarchy

set_instance_assignment -name NOC_READ_BANDWIDTH 6.4 -from noc_init|intel_noc_initiator_inst|iniu_0|initiator_inst_0 -to emif_io96b_ddr5comp_0|emif_io96b_ddr5comp_inst|emif_arch_top|t0.tniu_0|tniu_0|target_0.target_inst_0

Automatic upgrade for HPS EMIF IP is not working.

Due to a problem with the Quartus® Prime software and the packaged subsystem flow of the HPS EMIF IP for Agilex™ 7 M-series, the automatic upgrade mechanism fails when trying to update the HPS EMIF IP from an older version of the Quartus® Prime software to the latest version.

To work around this problem, you need to update all affected parameters within the HPS EMIF IP manually, to an allowed value for the latest version of the Quartus® Prime software. For additional details, refer to Why does the automatic upgrade mechanism in the Quartus® Prime Software fail for the HPS EMIF IP? in the FPGA Knowledge Base.
Table 2.   Agilex™ 7 M-Series Fabric EMIF IP Speed Support Summary
      Max Rate (Mbps/MHz)   -1 -2 -3
Protocol Category Subcategory -1 -2 -3 Support Detail S 1 C T 3 H S 1 C T 3 H S 1 C T 3 H
DDR4 Memory Format Component 3200/1600 (1R) 3200/1600 (1R) 2666/1333 (1R)   X X X X X X X X X X X X
2666/1333 (2R) 2666/1333 (2R) 2400/1200 (2R)   X X X X X X X X X X X X
UDIMM 3200/1600 (1DPC 1R) 3200/1600 (1DPC 1R) 2666/1333 (1DPC 1R)   X X X X X X X X X X X X
2666/1333 (1DPC 2R) 2666/1333 (1DPC 2R) 2400/1200 (1DPC 2R)   X X X X X X X X X X X X
SODIMM 3200/1600 (1DPC 1R) 3200/1600 (1DPC 1R) 2666/1333 (1DPC 1R)   X X X X X X X X X X X X
2666/1333 (1DPC 2R) 2666/1333 (1DPC 2R) 2400/1200 (1DPC 2R)   X X X X X X X X X X X X
RDIMM 3200/1600 (1DPC 1R) 3200/1600 (1DPC 1R) 2666/1333 (1DPC 1R)   X X X X X X X X X X X X
2666/1333 (1DPC 2R) 2666/1333 (1DPC 2R) 2400/1200 (1DPC 2R)   X X X X X X X X X X X X
DDR5 Memory Format Component 5600/2800 (1R) 5600/2800 (1R) 4800/2400 (1R)   X X X X X X X X X X X X
5200/2600 (2R) 5200/2600 (2R) 4400/2200 (2R)   X X X X X X X X X X X X
UDIMM 5600/2800 (1DPC 1R) 5600/2800 (1DPC 1R) 4800/2400 (1DPC 1R)   X X X X X X X X X X X X
4800/2400 (1DPC 2R) 4800/2400 (1DPC 2R) 4400/2200 (1DPC 2R)   X X X X X X X X X X X X
SODIMM 5600/2800 (1DPC 1R) 5600/2800 (1DPC 1R) 4800/2400 (1DPC 1R)   X X X X X X X X X X X X
4800/2400 (1DPC 2R) 4800/2400 (1DPC 2R) 4400/2200 (1DPC 2R)   X X X X X X X X X X X X
RDIMM 5600/2800 (1DPC 1R) 5600/2800 (1DPC 1R) 4400/2200 (1DPC 1R)   X X X X X X X X X X X X
4800/2400 (1DPC 2R) 4800/2400 (1DPC 2R) 4000/2000 (1DPC 2R)   X X X X X X X X X X X X
LPDDR5 4 Memory Format Component 1ch x 16 / 2ch x 16 / 4ch x 16 5500/2750 (1R) 2 5500/2750 (1R) 2 4246/2123 (1R) 2   X X X X X X X X X X X X
4800/2400 (2R) 2 2800/2400 (2R) 2 3736/1868 (2R) 2   X X X X X X X X X X X X
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • An empty table cell indicates that the feature is not currently supported.
  • 1 = Supports VCS, QuestaSim, Xcelium and Riviera Pro.
  • 2 = Current performance in the Quartus® Prime software. Check the External Memory Interface Spec Estimator for production performance.
  • 3 = Timing is currently preliminary. It will be necessary to recompile designs in future releases.
  • 4 = Support for LPDDR5 on production devices will be enabled through a future Quartus® Prime patch.
Table 3.   Agilex™ 7 M-Series Fabric EMIF IP Feature Support Summary
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC, 32, 32+ECC X X X X X
SODIMM, UDIMM 2 X X X X X 2
RDIMM 2 X X X X X 2
Controller Hard controller X X X X X
3DS 3DS Not supported        
Design Example   X X X X X
DBI Read DBI          
Write DBI X X X X X
DM DM pins X X X X X
AXI access mode 3 Fabric sync mode X X X X X
Fabric async mode X X X X X
NoC X X X X X
Debug EMIF Toolkit X X X X X
Simulation Abstract X X      
Accurate X X      
Simulators 1 VCS * Abstract X X X X  
NoC Accurate X X X X  
VCS-MX * Abstract X X X X  
NoC Accurate X X X X  
ModelSim SE * Abstract X X X X  
NoC Accurate X X X X  
QuestaSim* Abstract X X X X  
NoC Accurate X X X X  
Xcelium* Abstract X X X X  
NoC Accurate X X X X  
Riviera-PRO* Abstract X X X X  
NoC Accurate X X X X  
DDR5 Interface Width 16, 16+ECC, 32, 32+ECC X X X X X
SODIMM, UDIMM X X X X X
RDIMM X X X X X
Controller Hard controller X X X X X
3DS 3DS Not supported        
Design Example   X X X X X
DM DM pins X X X X X
AXI access mode 3 Fabric sync mode X X X X X
Fabric async mode X X X X X
NoC X X X X X
Debug EMIF toolkit X X X X X
Simulation Abstract X X      
Accurate X X      
Simulators 1 VCS* Abstract X X X X  
NoC Accurate X X X X  
VCS-MX* Abstract X X X X  
NoC Accurate X X X X  
ModelSim SE* Abstract X X X X  
NoC Accurate X X X X  
QuestaSim* Abstract X X X X  
NoC Accurate X X X X  
Xcelium* Abstract X X X X  
NoC Accurate X X X X  
Riviera-PRO* Abstract X X X X  
NoC Accurate X X X X  
LPDDR5 Interface Width 32 X X X X X
16 X X X X X
Controller Hard controller X X X X X
Design Example   X X X X X
DM DM pins X X X X X
AXI access mode 3 Fabric sync mode X X X X X
Fabric async mode X X X X X
NoC X X X X X
Debug EMIF toolkit X X X X X
Simulation Abstract X X      
Accurate X X      
Simulators 1 VCS* Abstract X X X X  
NoC Accurate X X X X  
VCS-MX* Abstract X X X X  
NoC Accurate X X X X  
ModelSim SE* Abstract X X X X  
NoC Accurate X X X X X
QuestaSim* Abstract X X X X  
NoC Accurate X X X X X
Xcelium* Abstract X X X X  
NoC Accurate X X X X  
Riviera-PRO* Abstract X X X X  
NoC Accurate X X X X  
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 2 = Only supported in fabric sync AXI access mode.
  • 3 = AXI exclusive accesses are not supported.
  • Note: Address mirroring is handled by the controller when needed.
    .
Table 4.   Intel Agilex® 7 M-Series HPS EMIF IP Speed Support Summary
      Max Rate (Mbps/MHz)   -1 -2 -3
Protocol Category Subcategory -1 -2 -3 Support Detail S 1 C T 2 H S 1 C T 2 H S 1 C T 2 H
DDR4 Memory Format Component 3200/1600 (1R) 3200/1600 (1R) 2666/1333 (1R)   X X X X X X X X X X X X
2666/1333 (2R) 2666/1333 (2R) 2400/1200 (2R)   X X X X X X X X X X X X
DDR5 Memory Format Component 5600/2800 (1R) 5600/2800 (1R) 4800/2400 (1R)   X X X X X X X X X X X X
5200/2600 (2R) 5200/2600 (2R) 4400/2200 (2R)   X X X X X X X X X X X X
UDIMM 5600/2800 (1DPC 1R) 5600/2800 (1DPC 1R) 4800/2400 (1DPC 1R)   X X X X X X X X X X X X
4800/2400 (1DPC 2R) 4800/2400 (1DPC 2R) 4400/2200 (1DPC 2R)   X X X X X X X X X X X X
SODIMM 5600/2800 (1DPC 1R) 5600/2800 (1DPC 1R) 4800/2400 (1DPC 1R)   X X X X X X X X X X X X
4800/2400 (1DPC 2R) 4800/2400 (1DPC 2R) 4400/2200 (1DPC 2R)   X X X X X X X X X X X X
RDIMM 5600/2800 (1DPC 1R) 5600/2800 (1DPC 1R) 4400/2200 (1DPC 1R)   X X X X X X X X X X X X
4800/2400 (1DPC 2R) 4800/2400 (1DPC 2R) 4000/2000 (1DPC 2R)   X X X X X X X X X X X X
LPDDR5 3 Memory Format Component 1ch x 16 / 2ch x 16 / 4ch x 16 5500/2750 (1R) 5500/2750 (1R) 4246/2123 (1R)   X X X   X X X   X X X  
4800/2400 (2R) 2800/2400 (2R) 3736/1868 (2R)   X X X   X X X   X X X  
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • An empty table cell indicates that the feature is not currently supported.
  • 1 = Supports VCS and QuestaSim.
  • 2 = Timing is currently preliminary. It will be necessary to recompile designs in future releases.
  • 3 = Hardware support for LPDDR5 is not available in the Agilex™ 7 M-Series EMIF IP version 3.0.0, and will be available in a future release.
Table 5.   Intel Agilex® 7 M-Series HPS EMIF IP Feature Support Summary
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC, 32, 32+ECC X X X X X
Controller Hard controller X X X X X
Design Example   X X X X  
DBI Read DBI          
Write DBI X X X X X
DM DM pins X X X X X
AXI access mode 3 Fabric sync mode          
Fabric async mode          
NoC X X X X X
Debug EMIF Toolkit          
Simulation Abstract X        
Accurate X        
Simulators 1 VCS* Abstract X X X X  
NoC Accurate X X X X  
VCS-MX* Abstract X X X X  
NoC Accurate X X X X  
ModelSim SE* Abstract X X X X  
NoC Accurate X X X X  
QuestaSim* X X X X X  
X X X X X  
Xcelium*          
Aldec*          
DDR5 Interface Width 16, 16+ECC, 32, 32+ECC 2 X X X X X
SODIMM, UDIMM X X X X X
RDIMM         X
Controller Hard controller X X X X X
3DS 3DS Not supported        
Design Example   X X X X  
DM DM pins X X X X X
AXI access mode 3 Fabric sync mode          
Fabric async mode          
NoC X X X X X
Debug EMIF toolkit          
Simulation Abstract X        
Accurate X        
Simulators 1 VCS* Abstract X X X X  
NoC Accurate X X X X  
VCS-MX* Abstract X X X X  
NoC Accurate X X X X  
ModelSim SE* Abstract X X X X  
NoC Accurate X X X X  
QuestaSim* Abstract X X X X  
NoC Accurate X X X X  
Xcelium*          
Aldec*          
LPDDR5 Interface Width 32 X X X X  
16 X X X X  
Controller Hard controller X X X X  
Design Example   X X X X  
DBI Read DBI          
Write DBI X X X X  
DM DM pins X X X X  
AXI access mode 3 Fabric sync mode          
Fabric async mode          
NoC X X X X  
Debug EMIF toolkit          
Simulation Abstract X        
Accurate X        
Simulators 1 VCS* X X      
VCS-MX* X X      
ModelSim SE* X X      
QuestaSim* X X      
Xcelium*          
Aldec*          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 2 = DDR5 x32 or DDR5 x16 + ECC configurations will fail in hardware; this issue will be addressed in a future Quartus® Prime patch.
  • 3 = AXI exclusive accesses are not supported.
  • Note: Address mirroring is handled by the controller when needed.

Known Issues in this Version

For a list of known issues affecting this release of the External Memory Interfaces Agilex™ 7 M-Series FPGA IP, follow this link to the: FPGA Knowledge Base.

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