Article ID: 000101485 Content Type: Error Messages Last Reviewed: 06/26/2025

Why does the automatic upgrade mechanism in the Quartus® Prime Software fails for the HPS EMIF IP?

Environment

    Intel® Quartus® Prime Pro Edition
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Description

Due to a problem with the Quartus® Prime Software Tool and the packaged subsystem flow of the HPS EMIF IP for Agilex™ 7 FPGA M-series, Agilex™ 5 FPGA, Agilex™ 3 FPGA (any HPS EMIF that uses IO96B banks), the automatic upgrade mechanism will fail when trying to update the HPS EMIF IP from an older version of Quartus® Prime to the latest version of Quartus® Prime.

 

This issue is affecting upgrades for all HPS-EMIF designs because of how the IP was changed for 25.1, which includes completely changing the allowed value range of the CTRL_PERFORMANCE_PROFILE parameter, and certain memory timing parameters.  Any value that an older version of the IP assigned to this parameter will now be illegal in Quartus® Prime version 25.1.

Resolution

To workaround this problem, you will have to manually update all impacted parameters within the HPS EMIF IP to a legally allowed value for the latest Quartus® Prime versions.

 

Example 1:  Auto-Upgrade Failure with HPS EMIF with DDR5

Error messageemif_0_ddr5comp: Error: emif_0_ddr5comp: “Controller Performance Profile” (CTRL_PERFORMANCE_PROFILE) “default” is out of range: “Sequential Access Optimized” “Random Access Optimized” “Custom”

Solution:  Dive into Packaged Subsystem and manually change the value of parameter Controller Performance Profile from its old value to a legal value.  You can then return to the top-level and save/regenerate and all the other parameter settings from the previous version will copy over.

 

Example 2:  Auto-Upgrade Failure with HPS EMIF with DDR4

Error message:  emif_io96b_hps.emif_io96b_hps_inst: emif_0_ddr4comp: Error: emif_0_ddr4comp: “JEDEC Parameter”

Solution:  Perform the same workaround value range of the Controller Performance Profile parameter as mentioned in the previous example.

You will also need to choose “Upgrade in Editor”, then go into the “Advanced: Memory Timing Tab” and delete any entry in the override table for any of these parameters:

              tDQSS, tDSH, tDSS, tIH (Base), tIS (Base), tQSH, tWLH, tWLS

Once the above parameters and the CTRL_PERFORMANCE_PROFILE has been set to a legal value, everything can be saved and regenerated.

 

NOTE:  There may be other errors that need to be manually fixed based on parameterization if upgrading from other versions but the above broadly applies to bringing all previous versions into compliance with version 25.1

Related Products

This article applies to 1 products

Intel Agilex® 7 FPGAs and SoC FPGAs

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