2. FPGA AI Suite New Features and Enhancements
FPGA AI Suite Version 2025.3 adds the following new features and enhancements:
- The FPGA AI Suite is now available from the Quartus® Prime installer.
- Added the ability to update models when FPGA AI Suite IP is running in DDR-free mode.
- Added the ability to use the Quartus® Prime Platform Designer Parameter Editor to configure the width of the FPGA AI Suite IP DDR interface. Previously, you could set this value only by modifying the IP architecture file.
- Added full support for the lightweight, area-optimized hardware layout transform. This transform previously had beta-level support.
- Enhanced the performance estimator with a new "per-layer parallel efficiency" report. This report indicates how efficiently layers with some number of input/output channels can be processed given the CVEC and KVEC values for an architecture.
- Added a new hostless, JTAG-attach design example for the Agilex™ 3 FPGA C-Series Development Kit (DK-A3Y135BM16AEA).
- Mixed precision support is now production quality.