Agilex™ 7 General-Purpose I/O User Guide: M-Series

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ID 772138
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 M-Series General-Purpose I/O Overview 2. Agilex™ 7 M-Series GPIO-B Banks 3. Agilex™ 7 M-Series HPS I/O Banks 4. Agilex™ 7 M-Series SDM I/O Banks 5. Agilex™ 7 M-Series I/O Troubleshooting Guidelines 6. GPIO FPGA IP 7. Programmable I/O Features Description 8. Documentation Related to the Agilex™ 7 General-Purpose I/O User Guide: M-Series 9. Agilex™ 7 General-Purpose I/O User Guide: M-Series Archives 10. Document Revision History for the Agilex™ 7 General-Purpose I/O User Guide: M-Series
1. Agilex™ 7 M-Series General-Purpose I/O Overview x
1.1. Package Selection and I/O Vertical Migration Support 1.2. Types of I/O Banks
2. Agilex™ 7 M-Series GPIO-B Banks x
2.1. GPIO-B Bank Overview 2.2. GPIO-B Features 2.3. GPIO-B Implementation Guide 2.4. GPIO-B Termination 2.5. GPIO-B Design Guidelines 2.6. GPIO-B Simulation
2.1. GPIO-B Bank Overview x
2.1.1. GPIO-B Bank Structure 2.1.2. GPIO-B Buffers and Registers
2.2. GPIO-B Features x
Power Pins for the GPIO-B Buffers GPIO-B Buffer Features 2.2.1. Supported I/O Standards for GPIO-B Banks 2.2.2. GPIO-B Buffer Behavior 2.2.3. Programmable I/O Element Features for the GPIO-B Bank
2.2.3. Programmable I/O Element Features for the GPIO-B Bank x
2.2.3.1. Guidelines: Programmable Output Slew Rate Control 2.2.3.2. Guidelines: Programmable Pull-Up Resistor 2.2.3.3. Guidelines: Programmable De-Emphasis
2.3. GPIO-B Implementation Guide x
2.3.1. I/O Assignments with the Quartus® Prime Assignment Editor 2.3.2. Assigning Pin I/O Standards in the Quartus® Prime Pin Planner
2.3.1. I/O Assignments with the Quartus® Prime Assignment Editor x
2.3.1.1. Assigning Pin I/O Standards in the Quartus® Prime Assignment Editor 2.3.1.2. Assigning Programmable IOE Features in the Quartus® Prime Assignment Editor 2.3.1.3. GPIO-B Programmable IOE Features Assignment Names and Settings
2.4. GPIO-B Termination x
2.4.1. Single-Ended I/O Termination in M-Series Devices 2.4.2. True Differential Signaling I/O Termination in M-Series Devices
2.4.1. Single-Ended I/O Termination in M-Series Devices x
2.4.1.1. Single-Ended I/O Standards On-Chip Termination 2.4.1.2. OCT Calibration Block 2.4.1.3. Single-Ended I/O Standards External Termination 2.4.1.4. Single-Ended I/O Termination Implementation Guide
2.4.1.1. Single-Ended I/O Standards On-Chip Termination x
2.4.1.1.1. RS OCT 2.4.1.1.2. RT OCT 2.4.1.1.3. Dynamic OCT
2.4.1.4. Single-Ended I/O Termination Implementation Guide x
2.4.1.4.1. Configuring OCT Using the Assignment Editor 2.4.1.4.2. OCT Features Assignment Names and Settings
2.4.2. True Differential Signaling I/O Termination in M-Series Devices x
2.4.2.1. True Differential Signaling I/O Standard On-Chip Termination 2.4.2.2. True Differential Signaling I/O Standard External Termination
2.4.2.1. True Differential Signaling I/O Standard On-Chip Termination x
2.4.2.1.1. Configuring Differential Input RD OCT Using the Assignment Editor 2.4.2.1.2. Guidelines: Differential Input RD OCT
2.5. GPIO-B Design Guidelines x
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os 2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent GPIO-B Bank 2.5.3. VREF Sources and Input Standards Grouping 2.5.4. GPIO-B Pin Restrictions for External Memory Interfaces 2.5.5. RZQ Pin Requirement 2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages 2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check 2.5.8. Simultaneous Switching Noise 2.5.9. HPS Shared I/O Requirements 2.5.10. Clocking Requirements 2.5.11. Clock Restrictions for GPIO Interfaces 2.5.12. SDM Shared I/O Requirements 2.5.13. Unused Pins 2.5.14. VCCIO_PIO Supply for Unused GPIO-B Banks 2.5.15. GPIO-B Pins During Power Sequencing 2.5.16. Drive Strength Requirement for GPIO-B Input Pins 2.5.17. Maximum DC Current Restrictions 2.5.18. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility 2.5.19. Connection to True Differential Signaling Input Buffers During Device Reconfiguration 2.5.20. LVSTL700 I/O Standards Differential Pin Pair Requirements 2.5.21. Implementing a Pseudo Open Drain 2.5.22. Allowed Duration for Using RT OCT 2.5.23. Single-Ended Strobe Signal Differential Pin Pair Restriction 2.5.24. Implementing SLVS-400 Standard at 1.1 V VCCIO_PIO Sub-bank
2.6. GPIO-B Simulation x
2.6.1. IBIS Models—GPIO-B Support 2.6.2. IBIS-AMI Models 2.6.3. HSPICE* Models 2.6.4. Net Length Reports
3. Agilex™ 7 M-Series HPS I/O Banks x
3.1. HPS I/O Bank Overview 3.2. HPS I/O Features 3.3. HPS I/O Implementation Guide 3.4. HPS I/O Design Guidelines 3.5. HPS I/O Simulation
3.2. HPS I/O Features x
3.2.1. Supported I/O Standards for HPS I/O Banks 3.2.2. Programmable I/O Element Features for the HPS I/O Bank 3.2.3. HPS I/O Buffer Behavior
3.3. HPS I/O Implementation Guide x
3.3.1. Configuring Open Drain Feature for the HPS I/O 3.3.2. I/O Assignments with the Quartus® Prime Assignment Editor 3.3.3. Assigning Pin I/O Standards in the Quartus® Prime Pin Planner
3.3.2. I/O Assignments with the Quartus® Prime Assignment Editor x
3.3.2.1. Assigning Programmable IOE Features in the Quartus® Prime Assignment Editor 3.3.2.2. HPS I/O Programmable IOE Features Assignment Names and Settings
3.4. HPS I/O Design Guidelines x
3.4.1. HPS I/O Pins During Power Sequencing 3.4.2. HPS Shared I/O Requirements
3.5. HPS I/O Simulation x
3.5.1. IBIS Models—HPS I/O Support 3.5.2. Net Length Reports
4. Agilex™ 7 M-Series SDM I/O Banks x
4.1. SDM I/O Bank Overview 4.2. SDM I/O Features 4.3. SDM I/O Design Guidelines 4.4. SDM I/O Simulation
4.2. SDM I/O Features x
4.2.1. Supported I/O Standards for SDM I/O Banks 4.2.2. SDM I/O Buffer Behavior 4.2.3. I/O Standards and Features for Configuration Pins
4.3. SDM I/O Design Guidelines x
4.3.1. SDM I/O Pins During Power Sequencing 4.3.2. Avalon® Streaming Interface Dedicated Configuration Pins
4.4. SDM I/O Simulation x
4.4.1. IBIS Models—SDM I/O Support 4.4.2. Net Length Reports
6. GPIO FPGA IP x
6.1. Release Information for GPIO FPGA IP 6.2. Generating the GPIO FPGA IP 6.3. GPIO FPGA IP Parameter Settings 6.4. GPIO FPGA IP Interface Signals 6.5. GPIO FPGA IP Architecture 6.6. Verifying Resource Utilization and Design Performance 6.7. GPIO FPGA IP Timing 6.8. GPIO FPGA IP Design Examples
6.2. Generating the GPIO FPGA IP x
6.2.1. Altera® FPGA IP Generation Output
6.3. GPIO FPGA IP Parameter Settings x
6.3.1. Guideline: Swap datain_h and datain_l Ports in Migrated IP
6.4. GPIO FPGA IP Interface Signals x
6.4.1. Shared Signals 6.4.2. Data Bit-Order for Data Interface 6.4.3. Input and Output Bus High and Low Bits 6.4.4. Data Interface Signals and Corresponding Clocks
6.5. GPIO FPGA IP Architecture x
6.5.1. GPIO FPGA IP Data Paths 6.5.2. Register Packing
6.5.1. GPIO FPGA IP Data Paths x
6.5.1.1. Input Path 6.5.1.2. Output and Output Enable Paths
6.7. GPIO FPGA IP Timing x
6.7.1. Timing Components 6.7.2. Delay Elements 6.7.3. Timing Analysis 6.7.4. Timing Closure Guidelines
6.7.3. Timing Analysis x
6.7.3.1. Single Data Rate Input Register 6.7.3.2. DDIO Input Register 6.7.3.3. Single Data Rate Output Register 6.7.3.4. DDIO Output Register
6.8. GPIO FPGA IP Design Examples x
6.8.1. GPIO FPGA IP Synthesizable Quartus® Prime Design Example 6.8.2. GPIO FPGA IP Simulation Design Example
7. Programmable I/O Features Description x
7.1. Programmable Pre-Emphasis 7.2. Programmable De-Emphasis 7.3. Programmable Differential Output Voltage 7.4. Continuous Time Linear Equalization
1. Agilex™ 7 M-Series General-Purpose I/O Overview
2. Agilex™ 7 M-Series GPIO-B Banks
3. Agilex™ 7 M-Series HPS I/O Banks
4. Agilex™ 7 M-Series SDM I/O Banks
5. Agilex™ 7 M-Series I/O Troubleshooting Guidelines
6. GPIO FPGA IP
7. Programmable I/O Features Description
8. Documentation Related to the Agilex™ 7 General-Purpose I/O User Guide: M-Series
9. Agilex™ 7 General-Purpose I/O User Guide: M-Series Archives
10. Document Revision History for the Agilex™ 7 General-Purpose I/O User Guide: M-Series

2.2. GPIO-B Features

The I/O bank within the GPIO-B interface supports various differential and single-ended I/O standards to cater to different types of interfacing requirements.
  • Single-ended LVCMOS for general purpose I/O interfacing.
  • Single-ended and pseudo-differential voltage-referenced I/O standards for general purpose and external memory interfacing. The differential voltage-referenced output pins are not true differential output pins. The differential voltage-referenced I/O standards use two single-ended output pins with one of the output pins inverted.
  • True differential I/O buffer pairs using the True Differential Signaling and SLVS-400 I/O standards. The True Differential Signaling I/O standard is compatible with the LVDS, RSDS, Mini-LVDS, and LVPECL I/O standards. One true differential buffer pair forms a true differential channel.

Power Pins for the GPIO-B Buffers

The VCCIO_PIO and VCCPT pins power the I/O buffers located in the I/O bank within the GPIO-B interface.

GPIO-B Buffer Features

  • Single-ended non-voltage referenced and voltage-referenced I/O standards
  • Differential voltage-referenced I/O standards
  • True differential transmitters and receivers
  • Serializer/deserializer (SERDES)
  • Programmable slew rate
  • Programmable weak pull-up resistor
  • Programmable differential output voltage (VOD) for true differential output buffers
  • Programmable receiver equalization calibration
  • On-chip series termination (RS OCT)
  • On-chip parallel termination (RT OCT)
  • On-chip differential termination (RD OCT)
  • Dynamic on-chip parallel termination
  • Internally generated VREF
  • Programmable pre-emphasis for true differential output buffer
  • Programmable de-emphasis

Section Content
Supported I/O Standards for GPIO-B Banks
GPIO-B Buffer Behavior
Programmable I/O Element Features for the GPIO-B Bank

Level Two Title