1. Agilex™ 7 M-Series General-Purpose I/O Overview
2. Agilex™ 7 M-Series GPIO-B Banks
3. Agilex™ 7 M-Series HPS I/O Banks
4. Agilex™ 7 M-Series SDM I/O Banks
5. Agilex™ 7 M-Series I/O Troubleshooting Guidelines
6. GPIO FPGA IP
7. Programmable I/O Features Description
8. Documentation Related to the Agilex™ 7 General-Purpose I/O User Guide: M-Series
9. Agilex™ 7 General-Purpose I/O User Guide: M-Series Archives
10. Document Revision History for the Agilex™ 7 General-Purpose I/O User Guide: M-Series
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os
2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent GPIO-B Bank
2.5.3. VREF Sources and Input Standards Grouping
2.5.4. GPIO-B Pin Restrictions for External Memory Interfaces
2.5.5. RZQ Pin Requirement
2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.8. Simultaneous Switching Noise
2.5.9. HPS Shared I/O Requirements
2.5.10. Clocking Requirements
2.5.11. Clock Restrictions for GPIO Interfaces
2.5.12. SDM Shared I/O Requirements
2.5.13. Unused Pins
2.5.14. VCCIO_PIO Supply for Unused GPIO-B Banks
2.5.15. GPIO-B Pins During Power Sequencing
2.5.16. Drive Strength Requirement for GPIO-B Input Pins
2.5.17. Maximum DC Current Restrictions
2.5.18. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility
2.5.19. Connection to True Differential Signaling Input Buffers During Device Reconfiguration
2.5.20. LVSTL700 I/O Standards Differential Pin Pair Requirements
2.5.21. Implementing a Pseudo Open Drain
2.5.22. Allowed Duration for Using RT OCT
2.5.23. Single-Ended Strobe Signal Differential Pin Pair Restriction
2.5.24. Implementing SLVS-400 Standard at 1.1 V VCCIO_PIO Sub-bank
2.5.3. VREF Sources and Input Standards Grouping
Consider these VREF sources guidelines.
M-Series devices support internal VREF sources. Each I/O lane in the bank also has its own internal VREF generator. You can configure VREF generator in the External Memory Interfaces IP and PHY Lite for Parallel Interfaces IP.
In each I/O lane, adhere to the input standards grouping to ensure all input pins in the I/O lane use the same internal VREF source. If the mix of input standards in an I/O lane does not adhere to these groupings, Quartus® Prime displays error messages during design compilation.
Note: Although the following table lists the groups based on VREF, the final rules depend on implementation. For example, the PHY Lite interface uses one I/O standard per I/O lane. If you use HSTL-12 and SSTL-12 with the PHY Lite for Parallel Interfaces IP, assign each I/O standard in a different I/O lane.
Group | Input Standards Mix within I/O Lane |
---|---|
Group 1 |
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Group 2 |
|
Group 3 |
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Group 4 |
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Group 5 |
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