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1. Intel® FPGA AI Suite SoC Design Example User Guide
2. About the SoC Design Example
3. Intel® FPGA AI Suite SoC Design Example Quick Start Tutorial
4. Intel® FPGA AI Suite SoC Design Example Run Process
5. Intel® FPGA AI Suite SoC Design Example Build Process
6. Intel® FPGA AI Suite SoC Design Example Intel® Quartus® Prime System Architecture
7. Intel® FPGA AI Suite Soc Design Example Software Components
8. Streaming-to-Memory (S2M) Streaming Demonstration
A. Intel® FPGA AI Suite SoC Design Example User Guide Archives
B. Intel® FPGA AI Suite SoC Design Example User Guide Document Revision History
3.1. Initial Setup
3.2. Initializing a Work Directory
3.3. (Optional) Create an SD Card Image (.wic)
3.4. Writing the SD Card Image (.wic) to an SD Card
3.5. Preparing the Intel® Arria® 10 SX SoC FPGA Development Kit for the Intel® FPGA AI Suite SoC Design Example
3.6. Adding Compiled Graphs (AOT files) to the SD Card
3.7. Running the Demonstration Applications
3.5.1. Confirming Intel® Arria® 10 SX SoC FPGA Development Kit Board Settings
3.5.2. Connect the Intel® Arria® 10 SX SoC FPGA Development Kit to the Host Development System
3.5.3. Configuring the Intel® Arria® 10 SX SoC FPGA Development Kit UART Connection
3.5.4. Determining the Intel® Arria® 10 SX SoC FPGA Development Kit IP Address
7.1.1. Yocto Recipe: recipes-core/images/coredla-image.bb
7.1.2. Yocto Recipe: recipes-bsp/u-boot/u-boot-socfpga_%.bbapend
7.1.3. Yocto Recipe: recipes-drivers/msgdma-userio/msgdma-userio.bb
7.1.4. Yocto Recipe: recipes-drivers/uio-devices/uio-devices.bb
7.1.5. Yocto Recipe: recipes-kernel/linux/linux-socfpga-lts_5.15.bbappend
7.1.6. Yocto Recipe: wic
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6.5.1. The dla_0 Platform Designer Layer (dla.qsys)
The dla_0 layer contains the Intel® FPGA AI Suite IP and the Nios® V subsystem to provide streaming capabilities.
![](/content/dam/docs/us/en/768979/2023-1/lzf1678993620701.png)
When incorporating the Intel® FPGA AI Suite IP into a custom design, you can use the dla.qsys file as a starting point for the new design.