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2.3. Software Emulation of the FPGA AI Suite IP
The FPGA AI Suite includes a compiled software model of the FPGA AI Suite IP that is bit-accurate*. The emulation of the FPGA AI Suite IP is accessible through the OpenVINO™ plugin interface. This emulation models the numeric details of the IP, including the behavior of the block floating point numerics (when used).
The OpenVINO™ emulation plugin is enabled in the $COREDLA_ROOT/bin/plugins_emulation.xml plugins file. Because it uses the OpenVINO™ plugin architecture, it works with both the OpenVINO™ Python API and the C++ API. For an example that shows how to use emulation as the inference engine for the runtime dla_benchmark utility, refer to " Performing Inference Without an FPGA Board " in the FPGA AI Suite Getting Started Guide .
Because the emulation executes on the CPU and does not benefit from the FPGA acceleration, the emulation is much slower than inference on the FPGA. Typical inference times for a single image with ResNet50 are on the order of minutes of time. The inference speed varies dramatically depending on the architecture configuration and the graph.