FPGA AI Suite: Compiler Reference Manual

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ID 768972
Date 4/21/2025
Public
Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite Compiler Reference Manual 2. About the FPGA AI Suite Compiler 3. FPGA AI Suite Compiler Use Modes 4. FPGA AI Suite Compiler Command Line Options 5. Compiler Inputs and Outputs A. FPGA AI Suite Compiler Reference Manual Archives B. FPGA AI Suite Compiler Reference Manual Document Revision History
3. FPGA AI Suite Compiler Use Modes x
3.1. Compiling a Graph 3.2. Generating Artifacts for DDR-Free Operation 3.3. Estimating the Performance of a Graph 3.4. Estimating the Area and Power of an Architecture 3.5. Generating an Optimized Architecture
3.5. Generating an Optimized Architecture x
3.5.1. Generating an Architecture for Highest Performance 3.5.2. Generating an Architecture Optimized for a Frame Rate Target Value
4. FPGA AI Suite Compiler Command Line Options x
4.1. Inputs (dla_compiler Command Options) 4.2. Outputs (dla_compiler Command Options) 4.3. Reporting (dla_compiler Command Options) 4.4. Compilation Options (dla_compiler Command Options) 4.5. Architecture Options (dla_compiler Command Options) 4.6. Architecture Optimizer Options (dla_compiler Command Options) 4.7. Analyzer Tool Options (dla_compiler Command Options) 4.8. Miscellaneous Options (dla_compiler Command Options)
5. Compiler Inputs and Outputs x
5.1. FPGA AI Suite Input File Formats 5.2. FPGA AI Suite Compiler Graph Export Formats 5.3. The Partitioning Table Report 5.4. Model Analysis Reports
1. FPGA AI Suite Compiler Reference Manual
2. About the FPGA AI Suite Compiler
3. FPGA AI Suite Compiler Use Modes
4. FPGA AI Suite Compiler Command Line Options
5. Compiler Inputs and Outputs
A. FPGA AI Suite Compiler Reference Manual Archives
B. FPGA AI Suite Compiler Reference Manual Document Revision History

3.4. Estimating the Area and Power of an Architecture

To estimate the FPGA resource usage (area) and power consumption of an IP parameterization described by an architecture (.arch) file, use the --fanalyze-area option.

Running the FPGA AI Suite compiler with this option displays a report that shows area usage and generates a .ptc file (power-parameters.ptc) that you can open with the Power and Thermal Calculator. The Power and Thermal Calculator can then provide you with estimates for the static power, dynamic power, and total power consumption of the architecture. For more information about the Power and Thermal Calculator, refer to the Power and Thermal Calculator User Guide

Option

Description
--fanalyze-area [Required] Enable the area estimator and generate a .ptc file that you can open with the Power and Thermal Calculator to view power consumption estimates for the architecture.
--march [Required] The architecture parameterization to assume.
--fdump-area-report [Optional] Path specifying an output file for the area estimate summary.
--fdump-ptc-report [Optional] Path specifying a .ptc output file for use with the Power and Thermal Calculator.
The simplest command format for estimating the area of an FPGA AI Suite IP instance is as follows: 
dla_compiler \
   --fanalyze-area \
   --march <path to .arch file>

Example Command 

dla_compiler \
   --fanalyze-area \
   --march $COREDLA_ARCH/example_architectures/A10_Generic.arch
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