FPGA AI Suite: Compiler Reference Manual

Download PDF
ID 768972
Date 4/21/2025
Public

Visible to Intel only — GUID: zak1657207286897

Ixiasoft

View Details

Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite Compiler Reference Manual 2. About the FPGA AI Suite Compiler 3. FPGA AI Suite Compiler Use Modes 4. FPGA AI Suite Compiler Command Line Options 5. Compiler Inputs and Outputs A. FPGA AI Suite Compiler Reference Manual Archives B. FPGA AI Suite Compiler Reference Manual Document Revision History
3. FPGA AI Suite Compiler Use Modes x
3.1. Compiling a Graph 3.2. Generating Artifacts for DDR-Free Operation 3.3. Estimating the Performance of a Graph 3.4. Estimating the Area and Power of an Architecture 3.5. Generating an Optimized Architecture
3.5. Generating an Optimized Architecture x
3.5.1. Generating an Architecture for Highest Performance 3.5.2. Generating an Architecture Optimized for a Frame Rate Target Value
4. FPGA AI Suite Compiler Command Line Options x
4.1. Inputs (dla_compiler Command Options) 4.2. Outputs (dla_compiler Command Options) 4.3. Reporting (dla_compiler Command Options) 4.4. Compilation Options (dla_compiler Command Options) 4.5. Architecture Options (dla_compiler Command Options) 4.6. Architecture Optimizer Options (dla_compiler Command Options) 4.7. Analyzer Tool Options (dla_compiler Command Options) 4.8. Miscellaneous Options (dla_compiler Command Options)
5. Compiler Inputs and Outputs x
5.1. FPGA AI Suite Input File Formats 5.2. FPGA AI Suite Compiler Graph Export Formats 5.3. The Partitioning Table Report 5.4. Model Analysis Reports
1. FPGA AI Suite Compiler Reference Manual
2. About the FPGA AI Suite Compiler
3. FPGA AI Suite Compiler Use Modes
4. FPGA AI Suite Compiler Command Line Options
5. Compiler Inputs and Outputs
A. FPGA AI Suite Compiler Reference Manual Archives
B. FPGA AI Suite Compiler Reference Manual Document Revision History

4.7. Analyzer Tool Options (dla_compiler Command Options)

--fanalyze-area Option

Syntax
--fanalyze-area
Description
Set this option to have the compiler estimate the area of the specified architecture and generate a .ptc file that you can open with the Power and Thermal Calculator to see power usage estimates for the architecture.
Parsed As
(bool)

--fanalyze-performance Option

Syntax
--fanalyze-performance
Description
When this option is set, the compiler estimates the performance of the given graph on the specified architecture. The performance report provides the estimated kernel throughput for each network graph provided.

The compiler also estimates the average memory bandwidth and the memory requirements. The estimated memory requirement is typically an underestimate because it excludes the effects of memory fragmentation.

An example performance report is as follows: 
Graph reported throughput: 12.345678
Parsed As
(bool)

--fassumed-memory-bandwidth Option

Syntax
--fassumed-memory-bandwidth=<assumed_DDR_bandwidth_in_MB/s>
Description
The FPGA AI Suite IP throughput is directly correlated to the DDR bandwidth in your system. Use this option with the --fanalyze-performance option to have the compiler estimate the performance based on the assumed DDR bandwidth in MB/s. If the architecture file is a DDR-free architecture, do not set this option.
As an example, a performance report that includes this option (set as --fassumed-memory-bandwith=19200) includes the following line: 
ASSUMED DDR BANDWIDTH PER IP INSTANCE = 19200 MB/s
Parsed As
(double)

--fdump-area-report Option

Syntax
--fdump-area-report=<filepath>
Description
Optional output file for the area estimate.

This option also enables the --fanalyze-area option.

Parsed As
(string)

--fdump-performance-report Option

Syntax
--fdump-performance-report=<dump_performance>
Description
Optional output file for the performance estimate.

This option also enables the --fanalyze-performance option.

Parsed As
(string)

--fdump-ptc-report Option

Syntax
--fdump-ptc-report=<filepath>
Description
Optional output file for the Power and Thermal Calculator parameters files generated as part of the area estimation.

This option also enables the --fanalyze-area option.

Parsed As
(string)

--fdisplay-device Option

Syntax
--fdisplay-device
Description
The option enables displaying the device (for example, CPU or FPGA) for each subgraph for all networks.
Parsed As
(bool)
Level Two Title