FPGA AI Suite: Getting Started Guide

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ID 768970
Date 9/06/2024
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Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite Getting Started Guide 2. FPGA AI Suite Components 3. FPGA AI Suite Installation Overview 4. Installing the FPGA AI Suite Compiler and IP Generation Tools 5. Installing the FPGA AI Suite PCIe-Based Design Example Prerequisites 6. FPGA AI Suite Quick Start Tutorial 7. Running the Hostless DDR-Free Design Example A. FPGA AI Suite Getting Started Guide Archives B. FPGA AI Suite Getting Started Guide Document Revision History
3. FPGA AI Suite Installation Overview x
3.1. FPGA AI Suite Directory Structure
4. Installing the FPGA AI Suite Compiler and IP Generation Tools x
4.1. Supported FPGA Families 4.2. Operating System Prerequisites 4.3. Installing the FPGA AI Suite with System Package Management Tools 4.4. Installing OpenVINO™ Toolkit 4.5. Installing Quartus® Prime Pro Edition Software 4.6. Setting Required Environment Variables 4.7. Installing Intel® Threading Building Blocks (TBB) 4.8. Finalizing Your FPGA AI Suite Installation
4.3. Installing the FPGA AI Suite with System Package Management Tools x
4.3.1. Installing the FPGA AI Suite Into an Alternative Location
5. Installing the FPGA AI Suite PCIe-Based Design Example Prerequisites x
5.1. PCIe-based Design Example Hardware Prerequisites 5.2. PCIe-based Design Example Operating System Prerequisites 5.3. PCIe-based Design Example Software Prerequisites
5.3. PCIe-based Design Example Software Prerequisites x
5.3.1. Additional Software Prerequisites for the PCIe-based Design Example for Agilex™ 7 Devices
6. FPGA AI Suite Quick Start Tutorial x
6.1. Creating a Working Directory 6.2. Preparing OpenVINO™ Model Zoo 6.3. Preparing a Model 6.4. Running the Graph Compiler 6.5. Preparing an Image Set 6.6. Programming the FPGA Device 6.7. Performing Inference on the PCIe-Based Example Design 6.8. Building an FPGA Bitstream for the PCIe Example Design 6.9. Building the Example FPGA Bitstreams 6.10. Preparing a ResNet50 v1 Model 6.11. Performing Inference on the Inflated 3D (I3D) Graph 6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics 6.13. Performing Inference Without an FPGA Board
6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics x
6.12.1. Preparing a YOLOv3 Model 6.12.2. Preparing a COCO Validation Dataset and Annotations 6.12.3. Inference on YOLOv3 and Calculating Accuracy Scores
1. FPGA AI Suite Getting Started Guide
2. FPGA AI Suite Components
3. FPGA AI Suite Installation Overview
4. Installing the FPGA AI Suite Compiler and IP Generation Tools
5. Installing the FPGA AI Suite PCIe-Based Design Example Prerequisites
6. FPGA AI Suite Quick Start Tutorial
7. Running the Hostless DDR-Free Design Example
A. FPGA AI Suite Getting Started Guide Archives
B. FPGA AI Suite Getting Started Guide Document Revision History

4.5. Installing Quartus® Prime Pro Edition Software

The FPGA AI Suite is compatible with Quartus® Prime Pro Edition for Linux* Versions 19.2 - 24.2. FPGA AI Suite does not support Quartus® Prime Pro Edition for Windows*.

WSL 2 Restriction: In a Windows* Subsystem for Linux 2 (WSL 2) environment, you must install Quartus® Prime Pro Edition for Linux* in your WSL 2 environment. You cannot use a Quartus® Prime Pro Edition for Windows* installation with FPGA AI Suite in the WSL 2 environment on the same system.
Tip: When designing a solution with the FPGA AI Suite, use the latest supported version of Quartus® Prime Pro Edition.
Ensure that the QUARTUS_ROOTDIR environment variable is set correctly. For example, you can add the following to your ~/.bashrc file to set the target directory appropriately: 
export QUARTUS_ROOTDIR="<quartus_install_path>/quartus/"
Important:

The FPGA AI Suite design examples require specific versions of Quartus® Prime Pro Edition. This requirement applies only to the design examples and does not apply to the FPGA AI Suite IP and compiler. For the Quartus® Prime Pro Edition requirements for the design examples, refer to the following table:

Table 4.   Quartus® Prime Pro Edition Requirements for FPGA AI Suite Design Example
Design Example Quartus® Prime Pro Edition Requirement
PCIe-based design example for Agilex™ 7 devices Quartus® Prime Pro Edition Version 22.4 or later.

This document assumes that Version 24.2 is used.

SoC-based design example for Arria® 10 SX SoC devices Quartus® Prime Pro Edition Version 24.2

( Ashling* RiscFree* IDE for Intel® FPGAs is also required)

SoC-based design example for Agilex™ 7 I-Series SoC devices Quartus® Prime Pro Edition Version 24.2

( Ashling* RiscFree* IDE for Intel® FPGAs is also required)

Next Step

After installing Quartus® Prime Pro Edition, continue your installation with Setting Required Environment Variables.

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