Intel® FPGA AI Suite: Getting Started Guide

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ID 768970
Date 2/12/2024
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite Getting Started Guide 2. Intel® FPGA AI Suite Components 3. Intel® FPGA AI Suite Installation Overview 4. Installing the Intel® FPGA AI Suite Compiler and IP Generation Tools 5. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites 6. Intel® FPGA AI Suite Quick Start Tutorial A. Intel® FPGA AI Suite Getting Started Guide Archives B. Intel® FPGA AI Suite Getting Started Guide Document Revision History
3. Intel® FPGA AI Suite Installation Overview x
3.1. Intel® FPGA AI Suite Directory Structure
4. Installing the Intel® FPGA AI Suite Compiler and IP Generation Tools x
4.1. Supported FPGA Families 4.2. Operating System Prerequisites 4.3. Installing the Intel® FPGA AI Suite With System Package Management Tools 4.4. Installing OpenVINO™ Toolkit 4.5. Installing Intel® Quartus® Prime Pro Edition Software 4.6. Setting Required Environment Variables 4.7. Installing Intel® Threading Building Blocks (TBB) 4.8. Finalizing Your Intel® FPGA AI Suite Installation
4.3. Installing the Intel® FPGA AI Suite With System Package Management Tools x
4.3.1. Installing the Intel® FPGA AI Suite Into an Alternative Location
5. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites x
5.1. PCIe-based Design Example Hardware Prerequisites 5.2. PCIe-based Design Example Operating System Prerequisites 5.3. PCIe-based Design Example Software Prerequisites
5.3. PCIe-based Design Example Software Prerequisites x
5.3.1. Additional Software Prerequisites for the PCIe-based Design Example for Intel Agilex® 7 Devices 5.3.2. Additional Software Prerequisites for the PCIe-Based Design Example for Intel® Arria® 10 Devices
6. Intel® FPGA AI Suite Quick Start Tutorial x
6.1. Creating a Working Directory 6.2. Preparing OpenVINO™ Model Zoo 6.3. Preparing a Model 6.4. Running the Graph Compiler 6.5. Preparing an Image Set 6.6. Programming the FPGA Device 6.7. Performing Inference on the PCIe-Based Example Design 6.8. Building an FPGA Bitstream for the PCIe Example Design 6.9. Building the Example FPGA Bitstreams 6.10. Preparing a ResNet50 v1 Model 6.11. Performing Inference on the Inflated 3D (I3D) Graph 6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics
6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics x
6.12.1. Preparing a YOLOv3 Model 6.12.2. Preparing a COCO Validation Dataset and Annotations 6.12.3. Inference on YOLOv3 and Calculating Accuracy Scores
1. Intel® FPGA AI Suite Getting Started Guide
2. Intel® FPGA AI Suite Components
3. Intel® FPGA AI Suite Installation Overview
4. Installing the Intel® FPGA AI Suite Compiler and IP Generation Tools
5. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites
6. Intel® FPGA AI Suite Quick Start Tutorial
A. Intel® FPGA AI Suite Getting Started Guide Archives
B. Intel® FPGA AI Suite Getting Started Guide Document Revision History

5.1. PCIe-based Design Example Hardware Prerequisites

The minimum hardware requirement for the design examples are as follows:

  • Desktop computer or server with at least 1 free PCIe slot
  • Minimum RAM: 48GB
  • Minimum storage: 100GB SSD

Supported Boards

The PCIe-based design examples require one of the following boards:
  • Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GX FPGA

    This board is required by the PCIe-based design example for Intel® Arria® 10 devices.

  • Terasic* DE10-Agilex Development Board

    This board is required by the PCIe-based design example for Intel Agilex® 7 devices.

Additional Hardware Requirements for the Intel® PAC with Intel® Arria® 10 GX FPGA

The Intel® PAC with Intel® Arria® 10 GX FPGA requires server-level cooling with a dual-fan graphics card cooler or another appropriate fan.

Contact your Intel representative for specific cooling solution suggestions. Quote case 14016255788 when contacting your representative.

The Intel® PAC with Intel® Arria® 10 GX FPGA must have firmware version 1.2.1.

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