Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 3/31/2025
Public
Document Table of Contents

3.3.2. NoC Targets for Hard Processor Systems

Configure NoC targets for HPS using the External Memory Interfaces for HPS FPGA IP in Platform Designer. This IP always uses the NoC and does not have a bypass mode available. NoC targets for HPS can only connect to NoC initiators in Hard Processor System FPGA IP. For details on the External Memory Interfaces for HPS FPGA IP, refer to the External Memory Interfaces Agilex 7 M-Series FPGA IP User Guide.