F-Tile 50G Ethernet Intel® FPGA IP User Guide

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ID 758946
Date 1/20/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile 50G Ethernet Intel® FPGA IP User Guide 2. About this IP 3. Getting Started 4. F-tile 50G Ethernet Intel FPGA IP Parameters 5. Functional Description 6. Reset 7. Interfaces and Signal Descriptions 8. Control, Status, and Statistics Register Descriptions 9. Document Revision History for the F-Tile 50G Ethernet Intel® FPGA IP User Guide
2. About this IP x
2.1. Release Information 2.2. Features 2.3. Device Family Support
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Compiling the Full Design and Programming the FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the F-tile Reference and System PLL Clocks Intel® FPGA IP 3.5.3. Placement Settings for the 50G Ethernet Intel FPGA IP Core
5. Functional Description x
5.1. F-tile 50G Ethernet Intel FPGA IP Core Functional Description 5.2. User Interface to Ethernet Transmission
5.1. F-tile 50G Ethernet Intel FPGA IP Core Functional Description x
5.1.1. F-tile 50G Ethernet Intel FPGA IP TX MAC Datapath 5.1.2. 50 GbE TX PCS 5.1.3. F-tile 50G Ethernet Intel FPGA IP Core RX MAC Datapath 5.1.4. Link Fault Signaling Interface 5.1.5. 50 GbE RX PCS 5.1.6. Flow Control
5.1.1. F-tile 50G Ethernet Intel FPGA IP TX MAC Datapath x
5.1.1.1. Frame Padding 5.1.1.2. Preamble Insertion 5.1.1.3. Inter-Packet Gap Generation and Insertion 5.1.1.4. Frame Check Sequence (CRC32) Insertion
5.1.3. F-tile 50G Ethernet Intel FPGA IP Core RX MAC Datapath x
5.1.3.1. IP Core Preamble Processing 5.1.3.2. IP Core Malformed Packet Handling 5.1.3.3. Length/Type Field Processing
5.1.3.3. Length/Type Field Processing x
5.1.3.3.1. Length Checking 5.1.3.3.2. RX CRC Checking and Dynamic Forwarding
5.1.6. Flow Control x
5.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 5.1.6.2. XON/XOFF Pause Frames
5.2. User Interface to Ethernet Transmission x
5.2.1. Order of Transmission 5.2.2. Bit Order For TX and RX Datapaths
7. Interfaces and Signal Descriptions x
7.1. TX MAC Interface to User Logic 7.2. RX MAC Interface to User Logic 7.3. Transceivers 7.4. Transceiver Reconfiguration Signals 7.5. Avalon® Memory-Mapped Management Interface 7.6. Miscellaneous Status and Debug Signals 7.7. Flow Control Signals 7.8. Clock Signals 7.9. Reset Signals
8. Control, Status, and Statistics Register Descriptions x
8.1. TX MAC Registers 8.2. RX MAC Registers 8.3. Pause/PFC Flow Control Registers 8.4. Statistics Registers 8.5. Hard IP Registers
8.4. Statistics Registers x
8.4.1. Statistics Registers
1. About the F-Tile 50G Ethernet Intel® FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-tile 50G Ethernet Intel FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile 50G Ethernet Intel® FPGA IP User Guide

3.4. Generated File Structure

The Intel® Quartus® Prime Pro Edition software generates the following IP core output file structure.
Figure 5. IP Core Generated Files
Table 6.  IP Core Generated Files

File Name

Description

<your_ip>.ip

The Platform Designer system or top-level IP variation file. <your_ip> is the name that you give your IP variation.

<system>.sopcinfo

Describes the connections and IP component parameterizations in your Platform Designer system. You can parse its contents to get requirements when you develop software drivers for IP components.

Downstream tools such as the Nios® II Gen 2 tool chain use this file. The .sopcinfo file and the system.h file generated for the Nios® II Gen 2 tool chain include address map information for each slave relative to each master that accesses the slave. Different masters may have a different address map to access a particular slave component.

<your_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files.

This IP core does not support VHDL. However, the Intel® Quartus® Prime software generates this file.

<your_ip>.html

A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments.

<your_ip>_generation.rpt IP or Platform Designer generation log file. A summary of the messages during IP generation.
<your_ip>.qgsimc Lists simulation parameters to support incremental regeneration.
<your_ip>.qgsynthc Lists synthesis parameters to support incremental regeneration.
<your_ip>.qip

Contains all the required information about the IP component to integrate and compile the IP component in the Intel® Quartus® Prime Pro Edition software.

<your_ip>.csv Contains information about the upgrade status of the IP component.

<your_ip>.bsf

A Block Symbol File (.bsf) representation of the IP variation for use in Intel® Quartus® Prime Pro Edition Block Diagram Files (.bdf).

<your_ip>.spd

Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.

<your_ip>.ppf The Pin Planner File (.ppf) stores the port and node assignments for IP components created for use with the Pin Planner.
<your_ip>_bb.v You can use the Verilog black-box (_bb.v) file as an empty module declaration for use as a black box.
<your_ip>_inst.v and _inst.vhd HDL example instantiation template. You can copy and paste the contents of this file into your HDL file to instantiate the IP variation.

This IP core does not support VHDL. However, the Intel® Quartus® Prime Pro Edition software generates the _inst.vhd file.

<your_ip>.regmap If IP contains register information, .regmap file generates. The .regmap file describes the register map information of master and slave interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This enables register display views and user customizable statistics in the System Console.
<your_ip>.svd

Allows hard processor system (HPS) System Debug tools to view the register maps of peripherals connected to HPS within a Platform Designer system.

During synthesis, the .svd files for slave interfaces visible to System Console masters are stored in the .sof file in the debug section. System Console reads this section, which Platform Designer can query for register map information. For system slaves, Platform Designer can access the registers by name.

synth/ <your_ip>.v or < synth/ <your_ip>.vhd Top-level IP synthesis HDL files that instantiate each submodule or child IP core for synthesis.

This IP core does not support VHDL. However, the Intel® Quartus® Prime software generates this file.

sim/<your_ip>.v or .vhd

Top-level simulation files that instantiate each submodule or child IP core for simulation.

This IP core does not support VHDL. However, the Intel® Quartus® Prime Pro Edition software generates this file.

sim/ mentor/

Contains a ModelSim script msim_setup.tcl to set up and run a simulation.

sim/ aldec/

Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a simulation.

sim/ synopsys/vcs/

sim/ synopsys/vcsmx/

Contains a shell script vcs_setup.sh to set up and run a VCS® simulation.

Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file to set up and run a VCS MX® simulation.

sim/xcelium/

Contains a shell script xcelium_setup.sh and other setup files to set up and run an xcelium simulation.

<child IP cores>/ For each generated child IP core directory, Platform Designer generates synth/ and sim/ sub-directories.
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