Nios® V Processor Software Developer Handbook

ID 743810
Date 9/26/2022
Public

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6.6.6.2. Extra Logging Options

In addition to the default boot messages, logging options are incorporated in Intel FPGA logging. Each option is controlled by a C preprocessor symbol.
Table 23.  Intel FPGA Logging Options and Option Modifiers
Name Description
System clock log Purpose Prints out a message from the system clock interrupt handler at a specified interval. This indicates that the system is still running. The default interval is every 1 second.
Preprocessor symbol ALT_LOG_SYS_CLK_ON_FLAG_SETTING
Modifiers The system clock log has two modifiers, providing two different ways to specify the logging interval.
  • ALT_LOG_SYS_CLK_INTERVAL—Specifies the logging interval in system clock ticks. The default is <clock ticks per second>, that is, one second.
  • ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER—Specifies the logging interval in seconds. The default is 1. When you modify ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER, ALT_LOG_SYS_CLK_INTERVAL is recalculated.
Sample Output System Clock On 0

System Clock On 1

Write echo Purpose Every time alt_write() is called (normally, whenever characters are sent to stdout), the first <n> characters are echoed to a logging message. The message starts with the string "Write Echo:". <n> is specified with ALT_LOG_WRITE_ECHO_LEN. The default is 15 characters.
Preprocessor symbol ALT_LOG_WRITE_ON_FLAG_SETTING
Modifiers ALT_LOG_WRITE_ECHO_LEN—Number of characters to echo. Default is 15.
Sample Output Write Echo: Hello from Nios V
JTAG startup log Purpose At JTAG UART driver initialization, print out a line with the number of characters in the software transmit buffer followed by the JTAG UART control register contents. The number of characters, prefaced by the string "SW CirBuf", might be negative, because it is computed as (<tail_pointer> – <head_pointer>) on a circular buffer.

For more information about the JTAG UART control register fields, refer to the Embedded Peripherals IP User Guide.

Preprocessor symbol ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING
Modifiers None
Sample Output JTAG Startup Info: SW CirBuf = 0, HW FIFO wspace=64 AC=0 WI=0 RI=0 WE=0 RE=1
JTAG interval log Purpose Creates an alarm object to print out the same JTAG UART information as the JTAG startup log, but at a repeated interval. Default interval is 0.1 second, or 10 messages a second.
Preprocessor symbol ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING
Modifiers The JTAG interval log has two modifiers, providing two different ways to specify the logging interval.
  • ALT_LOG_JTAG_UART_TICKS—Logging interval in ticks. Default is <ticks_per_second> / 10.
  • ALT_LOG_JTAG_UART_TICKS_DIVISOR—Specifies the number of logs per second. The default is 10. When you modify ALT_LOG_JTAG_UART_TICKS_DIVISOR, ALT_LOG_JTAG_UART_TICKS is recalculated.
Sample Output JTAG Alarm: SW CirBuf = 0, HW FIFO wspace=45 AC=0 WI=0 RI=0 WE=0 RE=1
JTAG interrupt service routine (ISR) log Purpose Prints out a message every time the JTAG UART near-empty interrupt triggers. Message contains the same JTAG UART information as in the JTAG startup log.
Preprocessor symbol ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING
Modifiers None
Sample Output JTAG IRQ: SW CirBuf = -20, HW FIFO wspace=64 AC=0 WI=1 RI=0 WE=1 RE=1
Boot log Purpose Prints out messages tracing the software boot process. The boot log is turned on by default when Intel FPGA logging is enabled.
Preprocessor symbol ALT_LOG_BOOT_ON_FLAG_SETTING
Modifiers None
Sample Output For more information, refer to Enabling Logging.
Note: An option’s modifiers are meaningful only when the option is enabled.

Setting a preprocessor flag to 1 enables the corresponding option. Any value other than 1 disables the option.

Several options have modifiers, which are additional preprocessor symbols controlling details of how the options work. For example, the system clock log’s modifiers control the logging interval.