Triple-Speed Ethernet Agilex™ 7 FPGA IP Design Example User Guide
ID
741330
Date
7/25/2025
Public
2.6. Interface Signals
Signal | Direction | Description |
---|---|---|
ref_clk | Input | 50 MHz reference clock for configuring CSR registers. |
iopll_refclk | Input | 125 MHz reference clock for LVDS I/O. |
serial_txp | Output | Positive signal for the transmitter serial data. |
serial_txn | Output | Negative signal for the transmitter serial data. |
serial_rxp | Input | Positive signal for the receiver serial data. |
serial_rxn | Input | Negative signal for the receiver serial data. |