Questa* Intel® FPGA Edition Simulation User Guide

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ID 730191
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Introduction to the Questa* Intel® FPGA Edition Simulator 3. Intel FPGA Simulation Basics 4. Simulating with Questa* Intel® FPGA Edition 5. Revision History for Questa Intel FPGA Edition Simulation User Guide A. Intel® Quartus® Prime Pro Edition User Guides
2. Introduction to the Questa* Intel® FPGA Edition Simulator x
2.1. Simulator Versions and Licensing 2.2. Accessing Siemens EDA-Provided Simulator Documentation 2.3. Document Prerequisites
2.1. Simulator Versions and Licensing x
2.1.1. Comparing Simulator Versions
3. Intel FPGA Simulation Basics x
3.1. Intel FPGA Simulation Essential Elements 3.2. Overview of Simulation Tool Flow 3.3. Simulation Tool Flow 3.4. Supported Simulation Types and Hardware Description Languages
3.2. Overview of Simulation Tool Flow x
3.2.1. Compilation Stage 3.2.2. Elaboration Stage 3.2.3. Simulation Stage
3.3. Simulation Tool Flow x
3.3.1. Specifying Logical Libraries 3.3.2. Compiling Files Into Library Directories 3.3.3. The Intel® Quartus® Prime Simulation Library 3.3.4. Understanding Elaboration 3.3.5. Commands To Configure and Run Simulation 3.3.6. Intel FPGA Simulation Generic Workflow
3.3.1. Specifying Logical Libraries x
3.3.1.1. Why Do We Need Logical Library Names?
3.3.2. Compiling Files Into Library Directories x
3.3.2.1. Inputs to Compilation Commands 3.3.2.2. Order of Files for Compilation Commands 3.3.2.3. Compilation Command Line Options 3.3.2.4. Module Definitions in Library Directories
3.3.3. The Intel® Quartus® Prime Simulation Library x
3.3.3.1. The Intel® Quartus® Prime Simulation Library Compiler 3.3.3.2. Running the Simulation Library Compiler in a Terminal 3.3.3.3. Running the Simulation Library Compiler in the GUI 3.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
3.3.4. Understanding Elaboration x
3.3.4.1. Elaboration Binding Phase 3.3.4.2. Elaboration Checks 3.3.4.3. Elaboration Options
3.4. Supported Simulation Types and Hardware Description Languages x
3.4.1. Supported Simulation Types 3.4.2. Supported Hardware Description Languages
4. Simulating with Questa* Intel® FPGA Edition x
4.1. Types of Questa* Intel® FPGA Edition Commands 4.2. Commands to Invoke Questa* Intel® FPGA Edition 4.3. Commands to Compile, Elaborate, and Simulate 4.4. Why You Should Only Use Precompiled Questa Intel FPGA Edition Libraries 4.5. Generating a msim_setup.tcl Simulation Script for RTL Simulation 4.6. Performing RTL Simulation with Questa* Intel® FPGA Edition 4.7. Performing Gate-Level Simulation with Questa* Intel® FPGA Edition
4.3. Commands to Compile, Elaborate, and Simulate x
4.3.1. Compilation Command Examples 4.3.2. Finding Logical Library Names in Simulation Library Compiler Output 4.3.3. Elaboration Command Examples 4.3.4. Simulation Command Examples 4.3.5. Complete Tcl Script Example
4.3.1. Compilation Command Examples x
4.3.1.1. Compilation Example 1: Compile File foo.sv into a Logical Library 4.3.1.2. Compilation Example 2: Compile File design1.sv to Default Library (work) 4.3.1.3. Compilation Example 3: Compile All .sv Files into Logical Library foo 4.3.1.4. Compilation Example 4: Compile File foo.sv into Work with Verilog Macro FAST Set to 1 4.3.1.5. Compilation Example 5: File my_pkg.sv Defines SystemVerilog Package my_pkg and File foo.sv Imports my_pkg 4.3.1.6. Compilation Example 6: File my_pkg.sv Defines Systemverilog Package my_pkg and File foo.sv Imports my_pkg
4.3.3. Elaboration Command Examples x
4.3.3.1. Elaboration Example 1: Elaborate the Test Top-level Testbench Module 4.3.3.2. Elaboration Example 2: Elaborate the Test Top-level Testbench Module and Preserve All Signals 4.3.3.3. Elaboration Example 3: Elaborate Top-Level Testbench Module my_test
4.3.4. Simulation Command Examples x
4.3.4.1. Simulation Example 1: Run Simulation Until the End, while Capturing Waveforms of All Top-Level Signals in the Testbench 4.3.4.2. Simulation Example 2: Run Simulation for 30 Milliseconds, while Capturing Waveforms of All Top-Level Signals in the Hierarchy 4.3.4.3. Simulation Example 3: Run Simulation Until the End, while Capturing Waveforms of Top-Level Design Instance
4.5. Generating a msim_setup.tcl Simulation Script for RTL Simulation x
4.5.1. Commands Defined in msim_setup.tcl 4.5.2. Example Using msim_setup.tcl without Customization 4.5.3. Example my_sim.tcl Simulation Script 4.5.4. Passing In Custom Compilation and Elaboration Options for msim_setup.tcl 4.5.5. Finding All Custom Variables
4.6. Performing RTL Simulation with Questa* Intel® FPGA Edition x
4.6.1. Simulating an RTL Design without IP Variants or Platform Designer Systems 4.6.2. Simulating an RTL Design that has IP Variants or Platform Designer Systems
4.6.2. Simulating an RTL Design that has IP Variants or Platform Designer Systems x
4.6.2.1. Compilation Stage - Simulation with IP 4.6.2.2. Elaboration Stage - Simulation with IP 4.6.2.3. Simulation Stage - Simulation with IP
4.6.2.1. Compilation Stage - Simulation with IP x
4.6.2.1.1. Customizing the Generated Simulation Script
4.7. Performing Gate-Level Simulation with Questa* Intel® FPGA Edition x
4.7.1. Post-Synthesis and Post-Fit Netlists for Simulation 4.7.2. Files Required for Gate-Level Simulation 4.7.3. Step 1: Generate Gate-Level Netlists for Simulation 4.7.4. Step 2: Identify Simulation Files and Compilation Options for Gate-Level Simulation 4.7.5. Step 3: Determine Elaboration Options for Gate-Level Simulation 4.7.6. Step 4: Assemble and Run the Gate-Level Simulation Script
5. Revision History for Questa Intel FPGA Edition Simulation User Guide x
5.1. Questa Intel FPGA Edition Simulation User Guide Archive
1. Answers to Top FAQs
2. Introduction to the Questa* Intel® FPGA Edition Simulator
3. Intel FPGA Simulation Basics
4. Simulating with Questa* Intel® FPGA Edition
5. Revision History for Questa Intel FPGA Edition Simulation User Guide
A. Intel® Quartus® Prime Pro Edition User Guides

4.7.1. Post-Synthesis and Post-Fit Netlists for Simulation

During compilation, the Intel® Quartus® Prime Compiler first synthesizes the design into a netlist (a set of module instances interconnected by wires) of low-level device family specific ATOM blocks. This is also known as technology mapping. ATOMs are logical representations of various Intel FPGA hardware blocks, such as lookup tables, DSPs, and memory blocks. The netlist that results from Intel® Quartus® Prime synthesis is the post-synthesis netlist. Refer to Intel Quartus Prime Simulation Library.

In the next stage of Intel® Quartus® Prime compilation, the Fitter takes the post-synthesis netlist as input, and produces a place and route solution for the ATOMs in the target FPGA that you specify. The netlist that results from place & route is the post-fit netlist.

The Intel® Quartus® Prime software can generate post-synthesis and post-fit netlists for simulation in Verilog HDL or VHDL format as Step 1: Generate Gate-Level Netlists for Simulation describes. Generally, The post-fit netlist has associated routing and cell (that is, ATOM) delays. However, the Intel® Quartus® Prime software does not support simulating a post-fit netlist with timing delays. In other words, the Intel® Quartus® Prime software supports post-fit functional simulation, but does not support post-fit timing simulation.

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