F-Tile JESD204B Intel® FPGA IP User Guide

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ID 723907
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. F-Tile JESD204B IP Quick Reference 2. About the F-Tile JESD204B Intel® FPGA IP 3. Getting Started 4. F-Tile JESD204B IP Functional Description 5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines 6. F-Tile JESD204B IP Debug Guidelines 7. F-Tile JESD204B Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile JESD204B Intel® FPGA IP User Guide
2. About the F-Tile JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. F-Tile JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. F-Tile JESD204B IP Design Considerations 3.8. F-Tile JESD204B Intel® FPGA IP Parameters 3.9. F-Tile JESD204B IP Component Files
3.6. Design Walkthrough x
3.6.1. Creating a New Intel® Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the F-Tile JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.7. F-Tile JESD204B IP Design Considerations x
3.7.1. Integrating the F-Tile JESD204B IP in Platform Designer 3.7.2. Pin Assignments 3.7.3. Adding External System PLL
4. F-Tile JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. System PLL Clock
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Register Map and Definition 4.7.3. Transmitter Registers 4.7.4. Receiver Registers
5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. F-Tile JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. F-Tile JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment
1. F-Tile JESD204B IP Quick Reference
2. About the F-Tile JESD204B Intel® FPGA IP
3. Getting Started
4. F-Tile JESD204B IP Functional Description
5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines
6. F-Tile JESD204B IP Debug Guidelines
7. F-Tile JESD204B Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile JESD204B Intel® FPGA IP User Guide

2.7. Performance and Resource Utilization

Table 5.   F-Tile JESD204B Intel® FPGA IP Performance
Device Family PMA Speed Grade FPGA Fabric Speed Grade Data Rate Link Clock FMAX (MHz)
Enable Hard PCS (Gbps) Enable Soft PCS (Gbps)
Intel Agilex® 7 (F-tile) 1 –1 Not supported 2.0 to 20.0 data_rate/40
–2 Not supported 2.0 to 19.2 data_rate/40
2 –2 Not supported 2.0 to 19.2 data_rate/40
–3 Not supported 2.0 to 16.7 data_rate/40
3 –3 Not supported 2.0 to 16.7 data_rate/40

All the variations for resource utilization are configured with the following parameter settings:

Table 6.  Parameter Settings To Obtain the Resource Utilization Data
Parameter Setting
F-Tile JESD204B Wrapper Base and PHY
F-Tile JESD204B Subclass 1
Data Rate 5 Gbps
Bonding Mode Non-bonded
Reference Clock Frequency 125.0 MHz
Octets per frame (F) 1
Enable Scrambler (SCR) Off
Enable Error Code Correction (ECC_EN) Off
Table 7.   F-Tile JESD204B IP Core Resource Utilization
Note: The resource utilization data are extracted from a full design which includes the Intel® FPGA Transceiver PHY Reset Controller IP core. Thus, the actual resource utilization for the F-Tile JESD204B IP core should be smaller by about 15 ALMs and 20 registers.
Device Family Data Path Number of Lanes (L) ALMs ALUTs Logic Registers Memory Block
Intel Agilex® 7

(F=1)

 RX 1 1839 2144 2442 1
2 2811.2 3184 3543 2
4 4693.5 5237 6198 4
8 8346.1 9144 9953 8
TX 1 1412.5 1549 2096 0
2 1754.8 1924 2371 0
4 1824.5 2531 3321 0
8 3679.4 3341 5002 0
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