1.6. F-Tile Ethernet Multirate Intel FPGA IP v6.0.0
| Quartus® Prime Version | Description | Impact |
|---|---|---|
| 23.1 | Updated Interface attributes for production silicon. | IP upgrade is required. |
| Added new parameter: Enable dedicated CDR Clock Output | Enables recovered CDR clock output for SyncE applications. | |
| Added new parameter: Include Deterministic Latency Interface | When enabled, generates the deterministic latency interface ports in FlexE mode. |
|
| Intel Agilex FPGAs renamed to Agilex™ 7 FPGAs. | — |