2.1. Port Numbering Scheme
2.2. Clock Signals
2.3. Reset Signals
2.4. Fractured MAC Segmented Interface for FGT Transceivers
2.5. Fractured MAC Segmented Interface for FHT Transceivers
2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers
2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers
2.8. Fractured MII PCS-Only Interface for FGT Transceivers
2.9. Fractured MII PCS-Only Interface for FHT Transceivers
2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers
2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers
2.12. MAC Flow Control Interface
2.13. Status Interface
2.14. Avalon® Memory-Mapped Reconfiguration Interfaces
2.15. Auto-Negotiation and Link Training Interface
2.16. Precision Time Protocol Interface
5.1. Precision Time Protocol
The Precision Time Protocol (PTP) provides 1588 Precision Time Protocol timestamp information as defined in the IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and Control System Standard. 1588 PTP logic generates 96-bit timestamp information for transmitted and received packets. The generated timestamps represent the time when the first bit after the Start of Frame Delimiter (SFD) byte crosses the FPGA serial pins (Medium Dependent Interface, MDI).
The detailed implementation, including the IP and PTP tile adapter connections and the PTP client flow, is described in the F-Tile Ethernet Intel® FPGA Hard IP User Guide.
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