F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

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ID 711009
Date 4/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Dynamic Reconfiguration Using QSF-driven Flow 4.4. Dynamic Reconfiguration Rules 4.5. Hardware States and Configuration Profiles 4.6. Nios® -Based Dynamic Reconfiguration Flow 4.7. Using the Tile Assignment Editor 4.8. Visualizing Dynamic Reconfiguration Group Placement 4.9. Assigning IP_COLOCATE Hierarchy 4.10. Example: Dynamic Reconfiguration with Multirate IP Flow 4.11. Example: Dynamic Reconfiguration Programming Sequence 4.12. Dynamic Reconfiguration Error Recovery Handling 4.13. Determining Profile Numbers 4.14. Master Clock Channel 4.15. Using the IP_RECONFIG_GROUP_PARENT QSF Assignment 4.16. Simulating the IP Core
4.6. Nios® -Based Dynamic Reconfiguration Flow x
4.6.1. Selecting the Nios® Data Memory Size
4.7. Using the Tile Assignment Editor x
4.7.1. Creating QSF Assignments 4.7.2. Generating the IP_Colocate QSF Assignment
4.14. Master Clock Channel x
4.14.1. Selecting the Master Clock Channel
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm 6.33. Dynamic Reconfiguration Local Error Status
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

4.11. Example: Dynamic Reconfiguration Programming Sequence

The following example depicts the programming sequence where 1x 100GE-4 profile is dynamically reconfigured to the 4x 25GE-1 profile. To disable the dynamic reconfiguration, set the next profile to 0x0.
For this example, the profiles were defined as:
  • 100GE-4: Profile 1
  • 25GE-1_0: Profile 4
  • 25GE-1_1: Profile 5
  • 25GE-1_2: Profile 6
  • 25GE-1_3: Profile 7
Follow this programming sequence:
  1. Program the Dynamic Reconfiguration Next Profile 0 register:
    • Set 0x04[18] = 1'b1: Disable CPI Sequence. Applicable for simulation only.
    • Set 0x04[15] = 1'b0: Disable profile 1.
    • Set 0x04[14:0] = 15'h1: Disable next profile to be profile 1x100GE-4 (profile 1).
  2. Program the Dynamic Reconfiguration Next Profile 1 register:
    • Set 0x08[15] = 1'b1: Enable next profile 1.
    • Set 0x08[14:0] = 15'h4: Set next profile to 25GE-1_0 (profile 4).
    • Set 0x08[31] = 1'b1: Enable next profile 2.
    • Set 0x08[30:16] = 15'h5: Set next profile to 25GE-1_1 (profile 5).
  3. Program the Dynamic Reconfiguration Next Profile 2 register:
    • Set 0x0C[15] = 1'b1: Enable next profile 3.
    • Set 0x0C[14:0] = 15'h6: Set next profile to 25GE-1_2 (profile 6).
    • Set 0x0C[31] = 1'b1: Enable next profile 4.
    • Set 0x0C[30:16] = 15'h7: Set next profile to 25GE-1_3 (profile 7).
  4. Program the Dynamic Reconfiguration Next Profile 3 register:
    • Set 0x10[15] = 1'b0: Disable next profile 5.
    • Set 0x10[14:0] = 15'h0: Set next profile to profile 0 to terminate the dynamic reconfiguration process.
    • Set 0x10[31] = 1'b0
    • Set 0x10[30:16] = 15'h0
Figure 20. Dynamic Reconfiguration Example: Registers Programming
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