F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide
ID
711009
Date
8/11/2025
Public
1. About the F-Tile Dynamic Reconfiguration Suite Core
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite User Guide
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles
4.2. Dynamic Reconfiguration QSF Settings
4.3. Dynamic Reconfiguration Using QSF-driven Flow
4.4. Dynamic Reconfiguration Rules
4.5. Hardware States and Configuration Profiles
4.6. Nios® -Based Dynamic Reconfiguration Flow
4.7. Using the Tile Assignment Editor
4.8. Visualizing Dynamic Reconfiguration Group Placement
4.9. Assigning IP_COLOCATE Hierarchy
4.10. Example: Dynamic Reconfiguration with Multirate IP Flow
4.11. Example: Dynamic Reconfiguration Programming Sequence
4.12. Dynamic Reconfiguration Error Recovery Handling
4.13. Determining Profile Numbers
4.14. Master Clock Channel
4.15. Using the IP_RECONFIG_GROUP_PARENT QSF Assignment
4.16. Simulating the IP Core
6.1. Dynamic Reconfiguration New Trigger
6.2. Dynamic Reconfiguration Next Profile 0
6.3. Dynamic Reconfiguration Next Profile 1
6.4. Dynamic Reconfiguration Next Profile 2
6.5. Dynamic Reconfiguration Next Profile 3
6.6. Dynamic Reconfiguration Next Profile 4
6.7. Dynamic Reconfiguration Next Profile 5
6.8. Dynamic Reconfiguration Next Profile 6
6.9. Dynamic Reconfiguration Next Profile 7
6.10. Dynamic Reconfiguration Next Profile 8
6.11. Dynamic Reconfiguration Next Profile 9
6.12. Dynamic Reconfiguration Next Profile 10
6.13. Dynamic Reconfiguration Next Profile 11
6.14. Dynamic Reconfiguration Next Profile 12
6.15. Dynamic Reconfiguration Next Profile 13
6.16. Dynamic Reconfiguration Next Profile 14
6.17. Dynamic Reconfiguration Next Profile 15
6.18. Dynamic Reconfiguration Next Profile 16
6.19. Dynamic Reconfiguration Next Profile 17
6.20. Dynamic Reconfiguration Next Profile 18
6.21. Dynamic Reconfiguration Next Profile 19
6.22. Dynamic Reconfiguration Avalon MM Timeout
6.23. Dynamic Reconfiguration TX Channel Reconfiguration
6.24. Dynamic Reconfiguration RX Channel Reconfiguration
6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment
6.26. Dynamic Reconfiguration TX Channel out of Reset
6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status
6.28. Dynamic Reconfiguration TX Channel Source Alarm
6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment
6.30. Dynamic Reconfiguration RX Channel out of Reset
6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status
6.32. Dynamic Reconfiguration RX Channel Source Alarm
6.33. Dynamic Reconfiguration Local Error Status
6.33. Dynamic Reconfiguration Local Error Status
Offset | 0x200 |
Addressing Mode | 32-bits |
Description | Dynamic Reconfiguration Local Bus Status Register |
Bit | Type | Reset | Description |
---|---|---|---|
31:24 | RO | 0 | Reserved |
23:16 | RO | 0 | Firmware Error State Displays the DR NIOS firmware unexpected termination and flagged out error message. DR NIOS returns to its initial state to trigger a new request. The NIOS firmware reports one of the following errors and returns to a known state in which it waits for a new trigger request from the Host and acts accordingly.
Selected Error state flags are described below:
Other ERROR_CODE values are reserved. When any of these errors occur during dynamic reconfiguration, the o_dr_error_status output port is set to 1. |
15:8 | RO | 0 | AVMM (GAVMM/MAIB) Timeout: Displays the AVMM timeout due to HIP and MAIB not responding. These sticky bits are automatically cleared when a new trigger request is made. [8] Displays the Global AVMM timeout event. [9] Displays the AIB AVMM1 timeout event. [15:10] Reserved When any of these errors occur during dynamic reconfiguration, the o_dr_error_status output port is set to 1. |
7:5 | RO | 0 | Reserved |
4:0 | RW | 5'h1 | Reserved. Do not modify this field. |