1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core
|Intel® Quartus® Prime Design Suite 23.2|
|IP Version 7.2.0|
- Setting up the required reference clocks. The system clock must be constant across all profiles in a selected dynamic reconfiguration group.
- Selecting the appropriate clocks input for each of the MAC, FEC, PCS, and transceiver blocks
- Setting the multiplexers to select the appropriate control and data path for MAC/PCS/PMA/FEC-direct modes
- Nios® -based dynamic reconfiguration: This flow includes the inter protocol switching, such as Ethernet to CPRI protocols, and intra protocol link characteristic changes, such as CPRI data rate changes. A client application or an Intel® Quartus® Prime Nios® utility triggers the dynamic reconfiguration. When triggered, the Nios® performs the low level configuration register programming for various functional blocks.
This document describes the NIOS-based dynamic reconfiguration through the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP.
To perform dynamic reconfiguration (DR), you must first configure the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP and then the associated protocol IP. You can use the F-Tile CPRI PHY Multirate Intel FPGA IP Core, F-Tile Ethernet Multirate Intel FPGA IP core, and F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP core. You can also use the standard, single-rate IPs as well.
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