1. Introduction 2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives 8. Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP

1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information

2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface

4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Dynamic Reconfiguration Rules 4.4. Hardware States and Configuration Profiles 4.5. Nios® -Based Dynamic Reconfiguration Flow 4.6. Visualizing Dynamic Reconfiguration Group Placement 4.7. Assigning IP_COLOCATE Hierarchy 4.8. Example: Dynamic Reconfiguration with Multirate IP Flow 4.9. Example: Dynamic Reconfiguration Programming Sequence

4.2.1. Dynamic Reconfiguration Using QSF-driven Flow

4.5.1. Selecting the Nios® Data Memory Size

5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability

6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm