F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 5. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 6. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
4.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 4.2. PMA/FEC Direct PHY Multirate Design Example: Registers
4.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
4.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
5. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
6. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 22.1

The F-Tile Dynamic Reconfiguration IP provides a simulation testbench and hardware design example that supports compilation and simulation. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

Intel® also provides a compilation-only example project that you can use to quickly estimate IP core area and timing.

Figure 1. Development Steps for the Design Example
The F-Tile Dynamic Reconfiguration design example supports the following design variants:
Table 1.  Supported Configuration
IP Protocol Base Variant Target Variants Supporting Dynamic Reconfiguration
CPRI 24G CPRI RS-FEC 24G CPRI RS-FEC
24G CPRI
12G CPRI RS-FEC
12G CPRI
10G CPRI RS-FEC
10G CPRI
9.8G CPRI
6G CPRI
4.9G CPRI
3G CPRI
2.4G CPRI
1.2G CPRI
Ethernet 25GE-1 25GE-1 RS-FEC
10GE-1
100GE-4 100GE-4
100GE-4 RS-FEC
100GE-2 RS-FEC
2x 50GE-1 RS-FEC
4x 25GE-1
4x 25GE-1 RS-FEC
400GE -8 1x 400GE-8 RS-FEC
2x 200GE-4 RS-FEC
4x 100GE-2 RS-FEC
PMA/FEC Direct PHY1 50G-1 53.1250Gbps PMA Direct
53.1250Gbps FEC Direct
25.7812Gbps PMA Direct
24.3330Gbps PMA Direct
10.3125Gbps PMA Direct
10.1376Gbps PMA Direct
9.8304Gbps PMA Direct
4.9152Gbps PMA Direct
2.4576Gbps PMA Direct
Related Information
1 Hardware support for the PMA/FEC Direct PHY Multirate Design Example will be available in a future version of the Intel® Quartus® Prime Pro Edition software.
Level Two Title