F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Release Notes

Download PDF
ID 710468
Date 4/03/2024
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Release Notes
1. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Release Notes x
1.1. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v9.0.0 1.2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v8.0.0 1.3. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v7.3.0 1.4. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.2.0 1.5. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.1.1 1.6. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.1.0 1.7. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.0.0 1.8. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v6.0.0 1.9. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v5.0.0 1.10. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v4.0.0 1.11. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives 1.12. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
1. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Release Notes

1.2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v8.0.0

Table 2.  v8.0.0 2023.12.04
Quartus® Prime Version Description Impact
23.4 Changed Nios® implementation from Nios® II to Nios® V IP's device utilization numbers have changed.
Changed the Recovery Enabled parameter default setting.

The parameter is now disabled by default.

When upgrading from the previous IP version, ensure the setting is consistent with your design intent.
Added the o_dr_fast_sim_clk_sel port For simulation only. This port can be used to speed up the simulation run times.
Level Two Title